MP3313 Rev.1.0

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7

8/2/2017

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Parameters

Symbol

Condition

Min

Typ

Max

Unit

Input logic low

0.4

V

Input logic high

1.3

V

Output logic low

0.4

V

SCLH clock frequency

1200

kHz

Set-up time for (repeated)

start condition

160

ns

Hold time for (repeated) start

condition

160

ns

Low time for SCLH clock

160

ns

High time for SCLH clock

60

ns

Data set-up time

10

ns

Data hold time

70

ns

Rise time of SCLH clock

10

40

ns

Rise time of SCLH clock

after repeated start and

acknowledge bit

10

80

ns

Fall time of SCLH clock

10

40

ns

Rise time of SDAH data

10

80

ns

Fall time of SDAH data

10

80

ns

Set-up time for stop condition

160

ns

Capacitive load for SDAH

line and SCLH line

100

pF

Capacitive load for

SDAH+SDA line and

SCLH+SCL line

400

pF

NOTES:

5) Matching is defined as the difference of the maximum to minimum current divided by 2 times average currents.

6) Guaranteed by design.

7) A device must provide a data hold time internally to bridge the undefined part between VIL and VIH of the falling edge of the SCLH signal.

An input circuit with a threshold as low as possible for the falling edge of SCLH signal minimizes the hold time.

8) For the bus line-load CB between 100pF and 400pF, the timing parameters must be increased linearly.

Sr

SDAH

SCLH

Sr

P

Sr: Repeated START Condition

P: STOP Condition