MP3331-2A SYNCHRONOUS BOOST FLASH LED DRIVER WITH I

MP3331 Rev. 1.02

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16

5/3/2016

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function tells the device how much flash current

can be drawn from the battery for the next flash.

Thus, it is possible to do a pre-flash function and

provide continuous stable flash current according

to IFL_MIN information (see Figure 13).

Figure 13: Pre-Flash Operation

VOUT-GND Short Protection

If VOUT<VIN-1V, the device stops switching and

disconnects the synchronous PMOS to avoid

drawing a very large current from the battery.

Once the device stops switching, set the

FT_VOSC bit to 1 and reset the mode setting.

The fault bit remains until read back or power

reset.

LED-GND Short Protection

If VLED < 1V & ILED > 25mA, the IC marks off

the current source and resets the mode setting

bits. Then the fault bit FT_LEDSC is set. The

fault bit FT_LEDSC is 1 until read back or power

reset.

LED Open Protection

If VOUT - VLED < 90mV & VOUT > 5.5V, the IC

stops switching and resets the mode setting bits.

Then the fault bits FT_OVP and FT_LEDOP are

set. The fault bits FT_OVP and FT_LEDOP are 1

until read back or power reset.

Output Over-Voltage Protection

If VOUT > 5.5V, the device stops switching and

resumes normal operation until VOUT drops

below 5.2V. The fault bit FT_OVP is 1 until read

back or power reset.

Junction Over-Temperature Protection

If Tj > 130℃, the flash current drops to the

current set by I_TX (if LED_OTAD = 1). The fault

bit FT_OTP is set. If Tj > 150℃, the device stops

switching and resets the mode setting. The fault

bit FT_OTP has to be cleared to 0 by read back

or power reset before the IC will re-start.

Time-Out Protection

If the device works in flash mode with hardware

and level sensitive enabled, the time-out

protection triggers when the STR high-level pulse

is longer than the timer set by FL_TIM. The

device stops switching and resets the mode

setting. The fault bit is 1 until read back or power

reset before the IC re-starts.

UVLO Protection

If the VIN drops below the UVLO threshold, the

device stops, and all the registers are reset to

default.

I

I

master sends a 7-bit address followed by an

eighth read (read: 1) or write (write: 0) bit. The

following bit indicates the register address

to/from which the data will be written/read (see

Figure 14 and the Tables below).

Figure 14: I