MP3378

– 4-CHANNEL WLED CONTROLLER PLUS BUCK CONVERTER

MP3378 Rev. 1.01

www.MonolithicPower.com

15

5/26/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2017 MPS. All Rights Reserved.

Buck Converter Section:

The step-down, switch-mode converter has built

in internal power MOSFETs and offers a very

compact

solution.

It

operates

in

a

fixed

frequency,

peak-current-control

mode

to

regulate the output voltage. A PWM cycle is

initiated by the internal clock. The integrated

high-side power MOSFET is turned on and

remains on until its current reaches the value

set

by

the

COMP_BUCK

voltage.

(COMP_BUCK

is one of the buck’s internal

control voltages; it is not the COMP pin.) When

the power switch is off, it remains off until the

next clock cycle starts. If the current in the

power

MOSFET

does

not

reach

the

COMP_BUCK set current value within 95

percent

of

one

PWM

period,

the

power

MOSFET is forced off.

Internal Regulator

Most of the internal circuitries are powered from

the 5 V internal regulator. This regulator takes

the VIN2 input and operates in the full VIN2

range. When VIN2 is greater than 5.0 V, the

output of the regulator is in full regulation. When

VIN2 is lower than 5.0 V, the output decreases;

a 0.1 uF ceramic capacitor for decoupling is

required.

Error Amplifier

The error amplifier compares the FB voltage

with the internal 0.8 V reference (REF) and

outputs a COMP_BUCK voltage, which is used

to control the power MOSFET current. The

optimized

internal

compensation

network

minimizes the external component count and

simplifies the control loop design.

AAM Operation

MP3378

has

advanced

asynchronous

modulation (AAM) power-save mode for light

load. Connect a resistor from AAM to GND to

set the AAM voltage. Under a heavy-load

When the clock goes high, the high-side power

reaches the value set by the COMP_BUCK

voltage. The internal clock re-sets every time

Under a light-load condition, the value of

the internal clock is blocked. This causes the

device to skip pulses for pulse frequency

modulation (PFM) mode, achieving the light-

load power save (see Figure 2).

S

R

Q

HS_driver

CLOCK

VIL_SENSE

1.1 pF

50 pF 400 K

RT

VREF

R1

R2

VOUT2

Figure 2

—Simplified AAM control logic

SYNC Control

The buck

converter

can

be synchronized

through SYNC to an external clock range from

250 kHz to 2 MHz. The internal clock

’s rising

edge is synchronized to the external clock

’s

falling

edge. The synchronized logic

high

voltage should be higher than 1.8 V. The

synchronized logic low voltage should be lower

than 0.6 V. The frequency of the external clock

should be higher than the frequency of the

internal clock. Otherwise the internal clock may

pulse high and turn on the high-side MOSFET

again.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the

buck converter from operating at an insufficient

supply voltage by monitoring the output voltage

of the internal regulator (VCC2). The UVLO

rising threshold is about 3.9 V while its falling

threshold is a consistent 3.25 V.

Internal Soft Start (SS)

Soft

start

is implemented to prevent the

converter output voltage from overshooting

during start up. When the chip starts up, the

internal circuitry generates a soft-start voltage

(SS) ramping up from 0 V. The soft-start period

lasts until the voltage on the soft-start capacitor

exceeds the reference voltage of 0.8 V. At this

point, the reference voltage takes over. The

soft-start time is set internally at around 1.5 ms.