AD8352

Data Sheet

Rev. C | Page 16 of 19

EVALUATION BOARD

An evaluation board is available for experimentation of various parameters such as gain, common-mode level, and distortion. The output

network can be configured for different loads via minor output component changes. The schematic and evaluation board artwork are

shown in Figure 38, Figure 39, and Figure 40. All discrete capacitors and resistors are Size 0402, except for C1 (3528-B).

Table 9. Evaluation Board Circuit Components and Functions

Component

Name

Function

Additional

Information

C8, C9, C10

Capacitors

C8, C9, and C10 are bypass capacitors.

C8 = C9 = C10 = 0.1 µF

Distortion

tuning

components

Distortion Adjustment Components. Allows for third-order distortion

adjustment HD3.

Typically, both are open

above 300 MHz

(microwave) multilayer

chip 402 capacitor

R1, R2, R3,

R4, R5, R6,

T2, C2, C3

Resistors,

transformer,

capacitors

Input Interface. R1 and R4 ground one side of the differential drive interface

for single-ended applications. T2 is a 1-to-1 impedance ratio balun to transform a

single-ended input into a balanced differential signal. R2 and R3 provide

a differential 50 Ω input termination. R5 and R6 can be increased to reduce

gain peaking when driving from a high source impedance. The 50 Ω

termination provides an insertion loss of 6 dB. C2 and C3 provide ac-coupling.

R1 = open, R2 = 25 Ω,

R3 = 25 Ω, R4 = 0 Ω,

R5 = 0 Ω, R6 = 0 Ω,

T2 = M/A-COM ETC1-1-13,

C2 = 0.1 μF, C3 = 0.1 μF

R7, R8, R9,

R11, R12,

R13, R14,

T1, C4, C5

Resistors,

transformer,

capacitors

Output Interface. R13 and R14 ground one side of the differential output

interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun to

transform a balanced differential signal to a single-ended signal. R8, R9, and

R12 are provided for generic placement of matching components. R7 and

R11 allow additional output series resistance when driving capacitive loads.

The evaluation board is configured to provide a 200 Ω to 50 Ω impedance

transformation with an insertion loss of 11.6 dB. C4 and C5 provide

ac-coupling. R7 and R11 provide additional series resistance when driving

capacitive loads.

R7 = 0 Ω, R8 = 86.6 Ω,

R9 = 57.6 Ω, R11 = 0 Ω,

R12 = 86.6 Ω, R13 = 0 Ω,

R14 = open,

T1 = M/A-COM ETC1-1-13,

C4 = 0.1 µF, C5 = 0.1 µF

Resistor

to Table 5 and Table 6 when selecting the gain resistor.

a gain of 10 dB

SW1, R18,

R19, R20

Switch,

resistors

Enable Interface. R10 connects the enable pin, ENB, to the supply for constant

enable operation. The enable function can be toggled by removing R10 and

using SW1 to switch between enable and disable modes.

SW1 = installed

R18 = R19 = R20 = 0 Ω

C1, C6, C7

Capacitors

Power Supply Decoupling. The supply decoupling consists of a 10 µF capacitor

(C1) to ground. C6 and C7 are bypass capacitors.

C1 = 10 µF, C6 = 0.1 µF,

C7 = 0.1 µF

T3, T4,

C11, C12

Transformer,

capacitors

Calibration Circuit. T3 and T4 are dummy baluns, which can be used to

calibrate the insertion loss across the transformers in the AD8352 signal chain.

T3 = T4 = M/A-COM ETC1-1-13

C11 = C12 = 0.1 µF

EVALUATION BOARD LOADING SCHEMES

The AD8352 evaluation board is characterized with two load

configurations representing the most common ADC input

resistance. The loads chosen are 200 Ω and 1000 Ω using a

broadband resistive match. The loading can be changed via R8,

R9, and R12 giving the flexibility to characterize the AD8352

evaluation board for the load in any given application. These

loads are inherently lossy and must be accounted for in overall

gain/loss for the entire evaluation board. Measure the gain of

the AD8352 with an oscilloscope using the following procedure

to determine the actual gain:

1. Measure the peak-to-peak voltage at the input node (C2 or C3).

2. Measure the peak-to-peak voltage at the output node (C4 or C5).

3. Compute gain using the following formula:

Gain = 20log(VOUT/VIN)

Table 10. Values Used for 200 Ω and 1000 Ω Loads

Component

200 Ω Load (Ω)

1000 Ω Load (Ω)

R8

86.6

487

R9

57.6

51.1

R12

86.6

487

SOLDERING INFORMATION

On the underside of the chip scale package, there is an exposed

compressed paddle. This paddle is internally connected to the

ground of the chip. Solder the paddle to the low impedance

ground plane on the PCB to ensure the specified electrical

performance and to provide thermal relief. To further reduce

thermal impedance, it is recommended that the ground planes

on all layers under the paddle be stitched together with vias.