LT8705 datasheet(7/24 Pages) LINER

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LT3840

3840fa

For more information www.linear.com/LT3840

pin FuncTions

AUXSW1 (Pin 1/Pin 36): AUXSW1 is a switching node of

the auxiliary bias supply. Connect the pin to the auxiliary

bias supply inductor.

PGND (Pin 2/Pin 38): PGND is the high current ground

return for the auxiliary bias supply. Connect PGND to the

negative terminal of the INTVCC decoupling capacitor and

to system ground.

AUXVIN (Pin 3/Pin 1): AUXVIN is the supply pin to the

auxiliary bias supply. Bypass the pin with a low ESR ca-

pacitor placed close to the pin and referenced to PGND.

SYNC (Pin 4/Pin 3): SYNC allows the LT3840 switching

frequency to be synchronized to an external clock. Set

the RT resistor such that the internal oscillator frequency

is 15% below the minimum external clock frequency. If

unused connect the SYNC pin to GND.

RT (Pin 5/Pin 4): An external resistor on RT sets the

switching frequency of the synchronous controller and

auxiliary bias supply.

TK/SS(Pin6/Pin6):TK/SSistheLT3840externaltracking

and soft-start input. The LT3840 regulates the VFB voltage

to the smaller of the internal reference or the voltage on the

TK/SS pin. An internal pull-up current source is connected

to this pin. A capacitor (CSS) to ground sets the ramp rate.

Alternatively, a resistor divider on another voltage supply

connected to this pin allows the LT3840 output to track

another supply during start-up. Leave the pin open if the

tracking and soft-start functions are unused.

FB (Pin 7/Pin 7): The regulator output voltage is set with

a resistor divider connected to FB. FB is also the input

for the output overvoltage and power good comparators.

VC (Pin 8/Pin 8): VC is the compensation node for the

output voltage regulation control loop.

PG (Pin 9/Pin 9): PG is a power good pin and is the open-

drain output of an internal comparator.

MODE (Pin 10/Pin 11): MODE is used to enable or disable

Burst Mode operation. Connect MODE to ground for Burst

Mode operation. Connect the pin to FB for pulse-skipping

mode. Connect MODE to INTVCC for continuous mode.

OVLO (Pin 11/Pin 12): OVLO has a precision threshold

with hysteresis to implement an accurate overvoltage

lockout (OVLO). Controller switching is disabled during

an overvoltage lockout (OVLO) event. INTVCC regulation

is maintained during an OVLO event. Connect the pin to

GND to disable the function.

UVLO (Pin 12/Pin 13): UVLO has a precision threshold

with hysteresis to implement an accurate undervoltage

lockout (UVLO). UVLO enables the controller switching.

Connect the pin to VIN to disable the function.

EN (Pin 13/Pin 14): EN has a precision IC enable threshold

with hysteresis. EN enables the auxiliary bias supply and

controller switching. Connect the pin to VIN to disable the

function. EN also has a lower threshold to put the LT3840

into a low current shutdown mode where all internal cir-

cuitry is disabled.

VIN (Pin 14/Pin 15): VIN provides an internal DC bias rail

and should be decoupled to GND with a low value (0.1µF),

low ESR capacitor located close to the pin.

GND (Pin 15, Exposed Pad Pin 29/Pin 17, Exposed Pad

Pin 39): Ground. Solder GND and the exposed pad directly

to the PCB ground plane.

IMON (Pin 16/Pin 18): The voltage on IMON represents

the average output current of the converter. A small value

capacitor filters the ripple voltage associated with the

inductor ripple current.

ICTRL (Pin 17/Pin 19): The maximum average output

current is programmed with a voltage applied to ICTRL.

If unused, leave floating.

ICOMP(Pin18/Pin20):Acapacitorandresistorconnected

to ICOMP compensates the average current limit circuit.

SENSE+ (Pin 19/Pin 21): SENSE+ is the positive input for

the differential current sense comparator.

SENSE– (Pin 20/Pin 22): SENSE– is the negative input for

the differential current sense comparator.

SW (Pin 21/Pin 24): SW is the high current return path

of the TG MOSFET driver and is externally connected to

the negative terminal of the BOOST capacitor.

(TSSOP/QFN)

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