LT8705 datasheet(18/24 Pages) LINER

18 / 24 page

LT3840

3840fa

For more information www.linear.com/LT3840

The soft-start capacitor is reset under fault conditions

including UVLO, EN, OVLO, overtemperature shutdown

and INTVCC UVLO. The soft-start pin is clamped through

a diode to the VFB pin. Therefore, the soft-start pin is reset

duringashort-circuitminimizingovershootuponrecovery.

EN, UVLO and OVLO

EN has a precision voltage threshold with hysteresis to

enable the LT3840 auxiliary bias supply and synchronous

controller. The pin is typically connected to VIN through a

resistor divider, however, it can be directly connected to

VIN. A lower voltage threshold on the EN pin is used to put

the LT3840 into a low quiescent current shutdown mode.

UVLO has a precision voltage threshold with hysteresis

to enable the LT3840 synchronous controller. The pin

is typically connected to VIN through a resistor divider,

however, it can be directly connected to VIN.

OVLO has a precision voltage threshold with hysteresis

to disable the LT3840 synchronous controller. The pin is

typicallyconnectedtoVINthrougharesistordivider.OVLO

can be directly connected to GND to disable the function.

Switching Frequency Synchronization

The oscillator can be synchronized to an external clock.

Set the RT resistor 15% below the lowest synchronized

frequency. The rising edge of the SYNC pin waveform

triggers the discharge of the internal oscillator capacitor.

If unused, connect the SYNC pin to GND.

Layout Considerations Checklist

The following is a list of recommended layout consider-

ations:

• Locate the VIN, AUXVIN, INTVCC, AUXBST and BOOST

pin bypass capacitors in close proximity to the LT3840.

• Create a solid GND plane, preferably on layer two of

the PCB.

• Minimize the hot loop. (See Figure 9)

• Use short wide traces for the MOSFET gate drivers (TG

andBG),aswellas,gatedrivesupplyandreturn(INTVCC

and BOOST, BGRTN and SW).

• Connect the FB pin directly to the feedback resistors,

independent of any other nodes (i.e. SENSE+).

• Locate the feedback resistors in close proximity to the

LT3840 FB pin.

• Route the SENSE– and SENSE+ traces close together

and keep as short as possible.

• SoldertheLT3840exposedpadtothePCB.Addmultiple

vias to connect the exposed pad to the GND plane.

• Per the manufacturer’s specification, add a sufficient

PCB pad around MOSFETs and inductor to dissipate

heat.

applicaTions inForMaTion

Figure 8. Precision EN, UVLO and OVLO Resistor Divider

3840 F08

EN, UVLO

OR OVLO

VIN

Figure 9. Hot Loop Layout for Synchronous Buck Regulator

3840 F09

HOT

LOOP

CIN

VIN

Resistors are chosen by first selecting RB. Then calculate

RA with the following formula:

RA =RB •

VTHRESHOLD

1.25V

– 1









VTHRESHOLD is the VIN referred voltage at which the supply

is enabled (UVLO and EN) or disabled (OVLO).

LT8705 数据表(PDF) 18 Page - Linear Technology

LT8705 数据表(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载