LTC2271

20

2271f

APPLICATIONS INFORMATION

REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)

D7

D6

D5

D4

D3

D2

D1

D0

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

OUTTEST

OUTMODE1

OUTMODE0

Bits 7-5

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 4

TERMON

LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0

Bit 3

OUTOFF

Output Disable Bit

0 = Digital Outputs are Enabled

1 = Digital Outputs are Disabled

Bit 2

OUTTEST

Digital Output Test Pattern Control Bit

0 = Digital Output Test Pattern Off

1 = Digital Output Test Pattern On

Bits 1-0

OUTMODE1:OUTMODE0

Digital Output Mode Control Bits

00 = 2-Lane Output Mode

01 = 4-Lane Output Mode

10 = 1-Lane Output Mode

11 = Not Used

REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)

D7

D6

D5

D4

D3

D2

D1

D0

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

Bits 7-0

TP15:TP8

Test Pattern Data Bits (MSB)

TP15:TP8 Set the Test Pattern for Data Bit 15 (MSB) Through Data Bit 8.

REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)

D7

D6

D5

D4

D3

D2

D1

D0

TP7

TP6

TP5

TP4

TP3

TP2

TP1

TP0

Bits 7-0

TP7:TP0

Test Pattern Data Bits (LSB)

TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).