13/21

MTC20154

Table 12. Linearity of ATU-R-RX

Table 13. Linearity of ATU-C-RX

A/D Converter

A pipeline architecture is used for the A/D converter.

Table 14. A/D Converter specifications

Power Supply Rejection

The noise on the power supplies for the RX-path must be lower than the following: < 50 mVrms in-band

white noise for any AVDD.

Figure 7. Power Supply Rejection

f1 (0.5 Vpd)

f2 (0.5 Vpd)

300 kHz

200 kHz

500 kHz

400 kHz

700 kHz

600 kHz

S/IM3

(AGC = 0 dB)

59.5 dB @100 kHz

53.5 dB @400 kHz

43.5 dB @700 kHz

42.5 dB @800 kHz

59.5 dB @300 kHz

48.0 dB @600 kHz

48.0 dB @500 kHz

42.5 dB @800 kHz

f1 (0,5 Vpd)

80 kHz

f2 (0,5 Vpd)

70 kHz

S/IM3

56.5 dB @60 kHz

(AGC = 20 dB)

56.5 dB @90 kHz

Number of bits:

13 bits

Minimum resolution of the A/D converter

11 bits

Linearity error of the A/D converter (range: -6 dB FS)

< 4 LSB (out of 13 bits)

Full scale input range:

1.1 Vpdif (+- 5 % @ 3.3 V)

Sampling rate:

8.832 MHz

Maximum attenuation at 1.1 MHz:

< 0.5 dB without in-band ripple

Latency:

5 sampling clock periods

1k

-40

dB

Hz

-50

-60

-70

10k 100k 1M 10M