STR710F datasheet(17/49 Pages) STMICROELECTRONICS

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STR71xF - INTRODUCTION

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1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to

Table 7, “Port Bit Configuration Table,” on page 26. The Port bit configuration at reset is

PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column

which specifies whether the pull-up or pull-down is enabled at reset

2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must

be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,”

on page 26) to be used by the External Memory Interface.

3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output

Address 0x0000 0000 using the External Memory Interface. To access memory banks greater

than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7, “Port

Bit Configuration Table,” on page 26).

136 B5

WE.1

8mA

External Memory Interface: active low MSB write ena-

ble output

137 C5

WE.0

8mA

External Memory Interface: active low LSB write enable

output

138 A3

V33

Supply voltage for digital I/Os

139 A2

VSS

Ground voltage for digital I/Os

140 D5

P0.5/S1.MOSI

I/O pu

4mA X

Port 0.5

SPI1: Master out/Slave In data

141 A4

P0.6/S1.SCLK

I/O pu

CT X 4mA X

Port 0.6

SPI1: Serial Clock

142 B4

P0.7/S1.SS

I/O pu

4mA X

Port 0.7

SPI1: Slave Select input active low

143 C4

P0.8/U0.RX/

U0.TX

I/O pd CT X4mA T

Port 0.8

UART0: Receive

Data input

UART0: Transmit data

output.

Note: This pin may be used for single wire UART (half

duplex) if programmed as Alternate Function Output.

The pin will be tri-stated except when UART transmis-

sion is in progress

144 B3

P0.9/U0.TX/

BOOT.0

I/O pd CT

4mA X

Port 0.9

Select Boot Con-

figuration input

UART0: Transmit data

output

Table 3. STR710 Pin Description

Pin n°

Pin Name

Input

Output

Main

function

(after

reset)

Alternate function

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