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HIP1012ACB 数据表(PDF) 5 Page - Renesas Technology Corp

部件名 HIP1012ACB
功能描述  Dual Power Distribution Controller
PDF  15 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HIP1012ACB 数据表(HTML) 5 Page - Renesas Technology Corp

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HIP1012A
FN4419 Rev 6.00
Page 5 of 15
March 2004
HIP1012A Description and Operation
The HIP1012A is a multifeatured dual power supply distribution
controller, including programmable current limiting regulation
and time to latch off. Additionally the HIP1012A operates both
as a +3.3V and 5V or a +5V and +12V power supply controller
with each mode having appropriate UnderVoltage (UV) fault
notification levels.
Upon initial power up HIP1012A can either isolate the voltage
supply from the load by holding the external N-Channel
MOSFET switches off or apply the supply rail voltage directly
to the load for true hot swap capability. In either case the
HIP1012A turns on in a soft start mode protecting the supply
rail from sudden current loading. If either PWRON pin is
pulled low the HIP1012A will be in true hot swap mode. Both
PWRON pins must be high to turn off the HIP1012A thus
isolating the power supply from the load through the external
FETs.
At turn-on, the gate capacitor of each external N-Channel
MOSFET is charged with a 10
A current source. These
capacitors create a programmable ramp (soft turn-on). A
charge pump supplies the gate drive for the 12V supply switch
driving that gate to 17V.
The load currents pass through two external current sense
resistors. When the voltage across either resistor exceeds the
user programmed Overcurrent (OC) voltage threshold value,
(see Table 1) the controller enters current regulation. At this
time the time-out capacitor, CTIM, starts charging with a 10A
current source and the controller enters the time out period.
The length of the time out period is set by the single external
capacitor (see Table 2) placed from the CTIM pin (pin 10) to
ground and is characterized by a lowered gate drive voltage to
the appropriate external N-Channel MOSFET. Once CTIM
charges to 2V, an internal comparator is tripped resulting in
both N-Channel MOSFETs being latched off.
Gate Turn-On Current
ION5V
CVG = 0.01F
8
10
12
A
3X Gate Discharge Current
3XdisI
CVG = 0.01F, PWRON = Low
0.5
0.75
-
A
5V Undervoltage Threshold
5VVUV
4.35
4.5
4.65
V
3.3V Undervoltage Threshold
3.3VVUV
2.65
2.8
2.95
V
3.3/5VG High Voltage
3/5VG
11.2
11.9
-
V
SUPPLY CURRENT AND IO SPECIFICATIONS
VDD Supply Current
IVDD
48
10
mA
VDD POR Rising Threshold
9.5
10.0
10.7
V
VDD POR Falling Threshold
9.3
9.8
10.3
V
Current Limit Time-Out
TILIM
CTIM = 0.1F16
20
24
ms
PWRON Pull-up Voltage
PWRN_V
PWRON pin open
1.8
2.4
3.2
V
PWRON Rising Threshold
PWR_Vth
1.1
1.5
2
V
PWRON Hysteresis
PWR_hys
0.1
0.2
0.3
V
PWRON Pull-Up Current
PWRN_I
60
80
100
A
Current Limit Time-Out Threshold (CTIM)CTIM_Vth
1.8
2
2.2
V
CTIM Charging Current
CTIM_I
8
10
12
A
CTIM Discharge Current
CTIM_disI
1.7
2.6
3.5
mA
CTIM Pull-Up Current
CTIM_disI
VCTIM = 8V
3.5
5
6.5
mA
RILIM Pin Current Source Output
RILIM_Io
90
100
110
A
Charge Pump Output Current
Qpmp_Io
CPUMP = 0.1F, CPUMP = 16V
320
560
800
A
Charge Pump Output Voltage
Qpmp_Vo
No load
17.2
17.4
-
V
Charge Pump Output Voltage - Loaded
Qpmp_VIo
Load current = 100
A
16.2
16.7
-
V
Charge Pump POR Rising Threshold
Qpmp+Vth
15.6
16
16.5
V
Charge Pump POR Falling Threshold
Qpmp-Vth
15.2
15.7
16.2
V
Electrical Specifications
VDD = 12V, CVG = 0.01F, CTIM = 0.1F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5,
TA = TJ = 0°C to 70°C, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS



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