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HIP2104FRAANZ 数据表(PDF) 16 Page - Renesas Technology Corp |
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HIP2104FRAANZ 数据表(HTML) 16 Page - Renesas Technology Corp |
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16 / 21 page ![]() HIP2103, HIP2104 FN8276 Rev 0.00 Page 16 of 21 November 27, 2013 Application Examples Above are examples (Figures 21, 22, and 23) of how the HIP2103, HIP2104 can be configured for various motor drive application with the HIP2104 supplying the 12V bias for the other HIP2103s and the VCC (3.3V) bias for the controller. VCen and VDen are used to turn on and off the internal linear regulators of the HIP2104. Because of entire switching of the bias supplies is implemented with logic, a signal switch, instead of a power switch, can be used to turn on and off the driver and controller. A switch debouncing delay of 1ms is provided on VDen and VCen. The external diode on VBATT is used to hold up the voltage on the VBAT input in the presence of severe ripple as usually seen on LI-ON batteries. In the case of the HIP2104, when VDen is low, the driver sections enters the Sleep Mode. When VCen is low, the bias to the controller is removed resulting with the lowest possible idle current in both the controller and the driver minimizing the drain on the battery when the motor drive is off. Sleep mode can also be initiated on the HIP2104 by driving HI and LI high simultaneously. In this case, the sleep mode current is substantially higher (~250µA) because the VDD and VCC outputs are still active. In the case of the HIP2103, Sleep Mode in the driver is initiated when HI and LI are both high simultaneously as previously described. If VDD is provided by an accompanying HIP2104, turning off the VDD output of the HIP2104 will also result with virtually no sleep current in the HIP2103 because there is no bias. For example, in the BLDC configuration, the sleep mode current will be ~5µA (in the HIP2104) and no current in both of the HIP2103s. Transients on the HS node An important operating condition that is frequently overlooked is the transient on the HS pin that occurs when the bridge FETs turn on or off. The Absolute Maximum negative transient (see page 5) allowed on the HS pin is -10V without any time restrictions on the duration of the transient. In most well designed PCBs, all that will be required is that the transient be less negative than -10V. FIGURE 23. BLDC (3-PHASE) MOTOR DRIVE TOPOLOGY Typical Applications µController HIP2104 VBAT VCen VCC VDD HI LI EPAD LO HS HO HB VDen VSS VBATT HI LI LO HS HO HB VSS HIP2103 EPAD VDD VDD HI LI LO HS HO HB VSS HIP2103 EPAD VDD BLDC Motor VBATT |
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