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AC208-DS03-R 数据表(PDF) 40 Page - Broadcom Corporation. |
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AC208-DS03-R 数据表(HTML) 40 Page - Broadcom Corporation. |
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40 / 58 page ![]() AC208 Preliminary Data Sheet 07/08/02 B roa dcom Page 32 PHY Registers Document AC208-DS04-405-R TRANSCEIVER MODE REGISTER Table 33: Transceiver Mode Register Register Bit Name Description Mode Default 23.15 Reserved RO 0 23.14 Reserved RO 0 23.13 Clk_rclk_save 1 = set rclk save mode. Rclk is hut off after 64 cycles of each packet RW 0 23.12 Reserved RO 0 23.11 Scramble disable 1 = disable scrambler RW 0 23.10 Serial bt enable 1 = enable serial bt mode RW 0 23.9 Pcsbp 1 = enable PCS bypass mode RW 0 23:8 Age timer en 1 = enable age timer in adaptation 0 = disable age timer in adaptation. RW 0 23.7 Reserved RO 0 23:6 Reserved RO 0 23.5 Force re-adapt 1 = force adaptation to re-adapt Writing a 1 to this bit forces adaptation to re-adapt. This bit is always read as 0. RO 0 23.[4:0] Dlock drop counter D lock drop counter RO XXXXX |
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