AC208-DS03-R datasheet(12/58 Pages) BOARDCOM

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AC208

Preliminary Data Sheet

07/08/02

B roa dcom

Page 4

Receive Function

Document

AC208-DS04-405-R

LINK MONITOR

Signal levels are detected through a squelch detection circuitry. A signal detect (SD) circuit follows the equalizer and is

asserted high when the peak detector detects a post-equalized signal with peak to ground voltage level larger than 400 mV.

This is approximately 40% of a normal signal voltage level. In addition, the energy level must be sustained longer than 2~3 µs

in order for the signal detects be asserted. It gets de-asserted approximately 1~2 µs after the energy level is consistently

less than 300 mV from peak to ground.

In 100BASE-TX mode, when no signal or invalid signal is detected on the receive pair, the link monitor enters in the link fail

state where only scrambled idle code is transmitted. When a valid signal is detected for a minimum period of time, the link

monitor enters a link pass state and transmit and receive functions are entered.

In 10BASE-T mode, a link-pulse detection circuit constantly monitors the RXIP/RXIN pins for the presence of valid link

pulses.

BASELINE WANDER COMPENSATION

The 100BASE-TX data stream is not always DC balanced. The transformer blocks the DC component of the incoming signal,

thus the DC offset of the differential receives inputs can wander. The shift in the signal levels, coupled with non-zero rise

and fall times of the serial stream can cause pulse-width distortion, creating jitter and possible increases in error rates.

Therefore, a DC restoration circuit is needed to compensate for the attenuation of DC component. The Transceiver

implemented is a patent-pending DC restoration circuit, unlike the traditional implementation; it does not need the feedback

information from the slicer and clock recovery. This not only simplifies the system/circuit design but also eliminates any

random/systematic offset on the receive path. In 10BASE-T mode, the baseline wander correction circuit is not required and

is bypassed.

CLOCK/DATA RECOVERY

The equalized MLT-3 signal passes through a slicer circuit that converts to NRZI format. The transceiver uses a mixed-signal

phase locked loop (PLL) to extract clock information of the incoming NRZI data. The extracted clock is used to re-time the

data stream and set the data boundaries. The transmit clock is locked to the 25-MHz clock input while the receive clock is

locked to the incoming data streams. When initial lock is achieved, the PLL switches to lock to the data stream, extracts a

125-MHz clock and uses that for bit framing to recover data. The recovered 125-MHz clock is also used to generate an

internal 25-MHz RX_CLK. The PLL requires no external components for its operation and has high noise immunity and low

jitter. It provides fast phase align (lock) to data in one transition and its data/clock acquisition time after power-on is less than

60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. When no

valid data is present (like when the SD is de-asserted), the PLL switches back to lock with TX_CLK and provides a

continuously running RX_CLK.

DECODER/DESCRAMBLER

The descrambler detects the state of the transmit Linear Feedback Shift Register (LFSR) by looking for a sequence

representing consecutive idle codes. The descrambler acquires lock with the data stream by recognizing IDLE bursts of 30

or more bits and locking to its de-ciphering Linear Feedback Shift Register (LFSR).

Once lock is acquired, the device operates with the inter-packet-gap (IPG) as low as 40 ns. Before lock occurs, the de-

scrambler requires a minimum of 720 nS of idle in between packet in order to acquire lock.

The deciphering logic also tracks the number of consecutive receive errors detected while RX_DV is asserted. Once the

error counter exceeds its limit (currently set to 64 consecutive errors), the logic assumes that lock has been lost, and the de-

cipher circuit resets itself. The process of regaining lock begins again.

Stream cipher de-scrambler is not used in 10BASE-T mode.

AC208-DS03-R 数据表(PDF) 12 Page - Broadcom Corporation.

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