ADL5511ACPZ-R7 datasheet(17/29 Pages) AD

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Data Sheet

ADL5511

Rev. C | Page 17 of 29

CIRCUIT DESCRIPTION

The ADL5511 employs a proprietary rectification technique

to strip off the carrier of an input signal to reveal the true

envelope. In this first detection stage, the carrier frequency

is doubled and an on-chip two-pole passive low-pass filter

accurately preserves the envelope and filters out the carrier.

The poles of this filter, as defined by the on-chip RC filters

(0.4 pF, 400 Ω, 0.8 pF, 250 Ω) values allow some carrier

leakthrough for common RF frequencies. This is to ensure

that maximum envelope bandwidth can be maintained.

For more details, see the Basic Connections section.

Figure 48. Block Diagram

The extracted envelope is further processed in two parallel

channels, one computing the rms value of the envelope and

the other transferring the envelope with appropriate scaling

to the envelope output.

ENVELOPE PROPAGATION DELAY

The delay specified in this data sheet is with no external

capacitor at the FLT2 and FLT3 pins. The delay through the

ADL5511, although very small, depends upon a number of

factors, notable of which are internal filter component values

and op amp compensation capacitors. The delay will vary from

part to part by approximately ±15% due to process variations.

In addition, the choice of external FLT2 and FLT3 values, as

well as load on the VNEV pin will increase the delay. In this

case, the delay variation will be dominated by the part-to-part

tolerance of the external capacitors.

RMS CIRCUIT DESCRIPTION

The rms processing is done using a proprietary translinear

technique. This method is a mathematically accurate rms

computing approach and achieves unprecedented rms

accuracies for complex modulation signals irrespective of

the crest factor of the input signal. An integrating filter

capacitor does the square-domain averaging. The VRMS

output can be expressed as

VRMS

−

∫ 2

(1)

Note that A is a scaling parameter that is decided on by the on-

chip resistor ratio, and there are no other scaling parameters

involved in this computation, which means that the rms output

is inherently free from any sources of error due to temperature,

supply, and process variation.

RMS FILTERING

The on-chip rms filtering corner is internally set by a 400 Ω

resistor and a 20 pF capacitor, yielding a corner frequency of

approximately 20 MHz. Whereas this filters out all carrier

frequencies, most of the modulation envelope is not filtered. For

adequate rms filtering, connect an external filter capacitor

between FLT4 (Pin 14) and VPOS (Pin 15). This capacitance

acts on the internal 400 Ω resistor (see Figure 48) to yield a new

corner frequency for the rms filter given by

)

400

(

−

Ω

RMS

FLT4

(2)

For example, a supply-referenced 0.1 µF capacitor on FLT4

reduces the corner frequency of the rms averaging circuit to

approximately 4 kHz.

RMS filtering has a direct impact on rms accuracy. For most

accurate detection, the rms filter corner should be low enough

to filter out most of the modulation content. This will corre-

spond to a corner frequency that is significantly lower than the

bandwidth of the signal being measured. See the Choosing a

Value for the RMS Averaging Capacitor (CFLT4) section for more

details and filtering options.

RFIN

ENBL

RMS

400Ω

20pF

ENVELOPE

VRMS

VENV

EREF

VPOS

400Ω

FLT1

FLT2

FLT3

COMM

FLT4

0.8pF

0.4pF

10kΩ

5pF

250Ω

100

Ω

ADL5511

BIAS AND POWER-

DOWN CONTROL

G = 1.7

G = 1.5

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