IMX7SCEC datasheet(39/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

DDRMC operation with the standards stated above is contingent upon the board DDR design adherence

to the DDR design and layout requirements stated in the hardware development guide for the i.MX 7

application processor.

4.5.2.1

LPDDR3 mode I/O DC parameters

Table 23. DC input logic level

Characteristics

Symbol

Min

Max

Unit

DC input logic high1

1 It is the relationship of the V

DDQ of the driving device and the VREF of the receiving device that determines noise margins.

However, in the case of VIH(DC) max (that is, input overdrive), it is the VDDQ of the receiving device that is referenced.

VIH(DC)

VREF +100

—

DC input logic low1

VIL(DC)

—VREF –100

Table 24. Output DC current drive

Characteristics

Symbol

Min

Max

Unit

Output minimum source DC current1

1 When DDS=[111] and without ZQ calibration.

IOH(DC)

–4

—

Output minimum sink DC current1

IOL(DC)

—

DC output high voltage(IOH = –0.1mA)

1,2

2 The values of V

OH and VOL are valid only for 1.2 V range.

VOH

0.9

× VDDQ

—V

DC output low voltage(IOL = 0.1mA)

1,2

VOL

—0.1

× VDDQ

Table 25. Input DC current

Characteristics

Symbol

Min

Max

Unit

High level input current1,2

1 The values of V

OH and VOL are valid only for 1.2 V range.

2 Driver Hi-Z and input power-down (PD=High)

IIH

–25

μA

Low level input current1,2

IIL

–25

μA

Table 26. LPDDR3 I/O DC electrical parameters

Parameters

Symbol

Test

Conditions

Min

Max

Unit

High-level output voltage

VOH

Ioh= -0.1mA

0.9

× OVDD

—

Low-level output voltage

VOL

Iol= 0.1mA

—

0.1

× OVDD

Input Reference Voltage

Vref

—

0.49

× OVDD

0.51

× OVDD

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