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IMX7SCEC 数据表(PDF) 111 Page - NXP Semiconductors |
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IMX7SCEC 数据表(HTML) 111 Page - NXP Semiconductors |
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111 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 111 4.10.15 USB PHY parameters This section describes the USB-OTG PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification is not applicable to Host port): • USB ENGINEERING CHANGE NOTICE — Title: 5V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0 • Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000 • USB ENGINEERING CHANGE NOTICE — Title: Pull-up/Pull-down resistors — Applies to: Universal Serial Bus Specification, Revision 2.0 • USB ENGINEERING CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0 • USB ENGINEERING CHANGE NOTICE — Title: USB 2.0 Phase Locked SOFs — Applies to: Universal Serial Bus Specification, Revision 2.0 • On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification — Revision 2.0, version 1.1a, July 27, 2010 • Battery Charging Specification (available from USB-IF) — Revision 1.2, December 7, 2010 4.10.15.1 USB_OTG*_REXT reference resistor connection The bias generation and impedance calibration process for the USB OTG PHYs requires connection of reference resistors 200 Ω 1% precision on each of USB_OTG1_REXT and USB_OTG2_REXT pads to ground. 4.10.15.2 USB_OTG_CHD_B USB battery charger detection external pullup resistor connection The usage and external resistor connection for the USB_OTG_CHD_B pin are described in Table 3, Table 7, and Section 4.7.3, “USB battery charger detection driver impedance.” |
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