AD8363ACPZ-R7 datasheet(15/29 Pages) AD

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Data Sheet

AD8363

Rev. B | Page 15 of 29

By forcing the previous identity through varying the VGA setpoint,

it is apparent that

RMS(VSIG) = √(Mean(VSIG2)) = √(VATG2) = VATG

(5)

Substituting the value of VSIG from Equation 2 results in

RMS(G0 × RFIN exp(−VSET/VGNS)) = VATG

(6)

When connected as a measurement device, VSET = VOUT. Solving

for VOUT as a function of RFIN

VOUT = VSLOPE × log10(RMS(RFIN)/VZ)

(7)

where:

VSLOPE is 1 V/decade (or 50 mV/dB).

VZ is the intercept voltage.

When RMS(RFIN) = VZ, because log10(1) = 0, this implies that

VOUT = 0 V, making the intercept the input that forces VOUT = 0 V.

VZ has been fixed to approximately 280 μV (approximately

−58 dBm, referred to 50 Ω) with a CW signal at 100 MHz.

In reality, the AD8363 does not respond to signals less than

~−56 dBm. This means that the intercept is an extrapolated

value outside the operating range of the device.

If desired, the effective value of VSLOPE can be altered by using

a resistor divider between VOUT and VSET. (Refer to the

Output Voltage Scaling section for more information.)

In most applications, the AGC loop is closed through the

setpoint interface and the VSET pin. In measurement mode,

VOUT is directly connected to VSET. (See the Measurement

Mode Basic Connections section for more information.) In

controller mode, a control voltage is applied to VSET and the

VOUT pin typically drives the control input of an amplification

or attenuation system. In this case, the voltage at the VSET pin

forces a signal amplitude at the RF inputs of the AD8363 that

balances the system through feedback. (See the Controller

Mode Basic Connections section for more information.)

RF INPUT INTERFACE

Figure 34 shows the connections of the RF inputs within

the AD8363. The input impedance is set primarily by an internal

50 Ω resistor connected between INHI and INLO. A dc level of

approximately half the supply voltage on each pin is established

internally. Either the INHI pin or the INLO pin can be used as

the single-ended RF input pin. (See the Choice of RF Input Pin

section.) If the dc levels at these pins are disturbed, performance

is compromised; therefore, signal coupling capacitors must be

connected from the input signal to INHI and INLO. The input

signal high-pass corner formed by the coupling capacitors and

the internal resistances is

fHIGH-PASS = 1/(2 × π × 50 × C)

(8)

where C is in farads and fHIGH-PASS is in hertz. The input coupling

capacitors must be large enough in value to pass the input signal

frequency of interest. The other input pin should be RF ac-coupled

to common (ground).

ESD ESD ESD ESD ESD ESD

ESD

2.5kΩ

50Ω

VBIAS

VPOS

INHI

INLO

Figure 34. RF Inputs Simplified Schematic

Extensive ESD protection is employed on the RF inputs, which

limits the maximum possible input amplitude to the AD8363.

CHOICE OF RF INPUT PIN

The dynamic range of the AD8363 can be optimized by choosing

the correct RF input pin for the intended frequency of operation.

Using INHI (Pin 14), users can obtain the best dynamic range at

frequencies up to 2.6 GHz. Above 2.6 GHz, it is recommended

that INLO (Pin 15) be used. At 2.6 GHz, the performance obtained

at the two inputs is approximately equal.

The AD8363 was designed with a single-ended RF drive in

mind. A balun can be used to drive INHI and INLO differentially,

but it is not necessary, and it does not result in improved

dynamic range.

SMALL SIGNAL LOOP RESPONSE

The AD8363 uses a VGA in a loop to force a squared RF signal

to be equal to a squared dc voltage. This nonlinear loop can be

simplified and solved for a small signal loop response. The low-

pass corner pole is given by

FreqLP ≈ 1.83 × ITGT/(CLPF)

(9)

where:

ITGT is in amperes.

CLPF is in farads.

FreqLP is in hertz.

ITGT is derived from VTGT; however, ITGT is a squared value of

VTGT multiplied by a transresistance, namely

ITGT = gm × VTGT2

(10)

gm is approximately 18.9 μs, so with VTGT equal to the typically

recommended 1.4 V, ITGT is approximately 37 μA. The value of

this current varies with temperature; therefore, the small signal

pole varies with temperature. However, because the RF squaring

circuit and dc squaring circuit track with temperature, there is no

temperature variation contribution to the absolute value of VOUT.

For CW signals,

FreqLP ≈ 67.7 × 10−6/(CLPF)

(11)

However, signals with large crest factors include low

pseudorandom frequency content that either needs to be

filtered out or sampled and averaged out. See the Choosing a

Value for CLPF section for more information.

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