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AD8363

Data Sheet

Rev. B | Page 16 of 29

TEMPERATURE SENSOR INTERFACE

The AD8363 provides a temperature sensor output with an

output voltage scaling factor of approximately 5 mV/°C. The

output is capable of sourcing 4 mA and sinking 50 μA maximum at

temperatures at or above 25°C. If additional current sink capability

is desired, an external resistor can be connected between the

TEMP and COMM pins. The typical output voltage at 25°C is

approximately 1.4 V.

TEMP

VPOS

COMM

INTERNAL

VPAT

12kΩ

4kΩ

Figure 35. TEMP Interface Simplified Schematic

VREF INTERFACE

The VREF pin provides an internally generated voltage reference.

The VREF voltage is a temperature stable 2.3 V reference that is

capable of sourcing 4 mA and sinking 50 μA maximum at

temperatures at or above 25°C. An external resistor can be

connected between the VREF and COMM pins to provide

additional current sink capability. The voltage on this pin can be

used to drive the TCM1, TCM2/PWDN, and VTGT pins, if desired.

INTERNAL

VOLTAGE

16kΩ

VREF

VPOS

COMM

Figure 36. VREF Interface Simplified Schematic

TEMPERATURE COMPENSATION INTERFACE

Proprietary techniques are used to maximize the temperature

stability of the AD8363. For optimal performance, the output

temperature drift must be compensated for using the TCM1 and

TCM2/PWDN pins. The absolute value of compensation varies

with frequency and VTGT. Table 4 shows the recommended voltages

for the TCM1 and TCM2/PWDN pins to maintain the best

temperature drift error over the rated temperature range (−40°C <

TA < 85°C) when driven single-ended and using a VTGT = 1.4 V.

Table 4. Recommended Voltages for TCM1 and TCM2/PWDN

Frequency

TCM1 (V)

TCM2/PWDN (V)

100 MHz

0.47

1.0

900 MHz

0.5

1.2

1.9 GHz

0.52

0.51

2.14 GHz

0.52

0.6

2.6 GHz

0.54

1.1

3.8 GHz

0.56

1.0

5.8 GHz

0.88

1.0

The values in Table 4 were chosen to give the best drift

performance at the high end of the usable dynamic range over

the −40°C to +85°C temperature range.

Compensating the device for the temperature drift using TCM1

and TCM2/PWDN allows for great flexibility and the user may

wish to modify these values to optimize for another amplitude

point in the dynamic range, for a different temperature range,

or for an operating frequency other than those shown in Table 4.

To find a new compensation point, VTCM1 and VTCM2 can be

swept while monitoring VOUT over the temperature at the

frequency and amplitude of interest. The optimal voltages for

VTCM1 and VTCM2 to achieve minimum temperature drift at a given

power and frequency are the values of VTCM1 and VTCM2 where

VOUT has minimum movement. See the AD8364 and ADL5513

data sheets for more information.

Varying VTCM1 and VTCM2 has only a very slight effect on VOUT at

device temperatures near 25°C; however, the compensation circuit

has more and more effect, and is more and more necessary for

best temperature drift performance, as the temperature departs

farther from 25°C.

Figure 37 shows the effect on temperature drift performance at

25°C and 85°C as VTCM1 is varied but VTCM2 is held constant at 0.6 V.

–1

–2

–3

–60

–50

–40

–30

–20

–10

RFIN (dBm)

25°C

85°C

VTCM1 = 0.62V

VTCM1 = 0.42V

Figure 37. Error vs. Input Amplitude over Stepped VTCM1 Values,

25oC and 85oC, 2.14 GHz, VTCM2 = 0.6 V

TCM1 primarily adjusts the intercept of the AD8363 at

temperature. In this way, TCM1 can be thought of as a coarse

adjustment to the compensation. Conversely, TCM2 performs a

fine adjustment. For this reason, it is advised that when searching

for compensation with VTCM1 and VTCM2, that VTCM1 be adjusted

first, and when best performance is found, VTCM2 can then be

adjusted for optimization.

It is evident from Figure 37 that the temperature compensation

circuit can be used to adjust for the lowest drift at any input

amplitude of choice. Though not shown in Figure 37, a similar

analysis can simultaneously be performed at −40°C, or any

other temperature within the operating range of the AD8363.

Performance varies slightly from device to device; therefore,

optimal VTCM1 and VTCM2 values must be arrived at statistically

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