AD8305

Data Sheet

Rev. C | Page 12 of 24

required to accommodate this situation (see the Using a

Negative Supply section).

resistance of 4.55 kΩ, formed by the parallel combination of a

6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the

VRDZ pin. When the VLOG pin is unloaded and the intercept

repositioning is disabled by grounding VRDZ, the output

(5)

resistive loading on VLOG lowers this slope and also result in

an overall scaling uncertainty due to the variability of the on-

chip resistors. Consequently, this practice is not recommended.

IREF may now be positioned at ground level by simply

grounding VSUM.

MANAGING INTERCEPT AND SLOPE

When using a single supply, VRDZ should be directly connected to

VREF to allow operation over the entire five-decade input current

range. As noted previously, this introduces an accurate offset

voltage of 0.8 V at the VLOG pin, equivalent to four decades,

resulting in a logarithmic transfer function that can be written as

(6)

The slope can be reduced by attaching a resistor to the VLOG

pin. This is strongly discouraged, in view of the fact that the on-

chip resistors do not ratio correctly to the added resistance. Also, it

is rare that one would want to lower the basic slope of 10 mV/dB; if

this is needed, it should be effected at the low impedance output

of the buffer, which is provided to avoid such miscalibration and

also allow higher slopes to be used.

The AD8305 buffer is essentially an uncommitted op amp with

rail-to-rail output swing, good load-driving capabilities, and a

unity-gain bandwidth of >12 MHz. In addition to allowing the

introduction of gain, using standard feedback networks and

to implement multipole low-pass filters, threshold detectors,

and a variety of other functions. Further details of these can be

found in the AD8304 data sheet.

RESPONSE TIME AND NOISE CONSIDERATIONS

The response time and output noise of the AD8305 are

Figure 15. The output low frequency voltage-noise spectral-

performance of translinear log amps can be found in the

AD8304 data sheet.

POWER SUPPLY SEQUENCING

Some applications may result in the presence of large input

signal current (>1 mA) prior to the AD8305 being powered on.

In such cases, it is recommended that power supply sequencing

be implemented such that the AD8305 is powered on prior to

the photodiode or current source.

In those applications where it is not possible to implement

supply sequencing, VSUM should be driven externally by a low

impedance source. In applications where a low impedance bias

source is not readily available, the circuit shown in Figure 34

can be used.

VPOS

VNEG

VSUM

2N2907

COMM

INPT

R1

C1

β

+

–

≈0.5V

Figure 34. VSUM Biasing Circuit for Applications Where Large Input Signals

Are Present Prior to AD8305 Power-On

The 2N2907 transistor used in Figure 34 is a common PNP-type

at the base of the transistor is ~0.5 V.

additional quiescent current for a 3 V supply under normal

operation. Larger resistor values may be used for this divider

network by choosing a transistor with a higher β than the

2N2907.

the AD8305 is off and a large input signal is being applied. Once

the AD8305 is powered on the voltage at VSUM is pulled down

to its nominal value of 0.5 V. The circuit in Figure 34 is tested

for 3 V to 5 V positive supplies over the full temperature range