AD8305

Data Sheet

Rev. C | Page 16 of 24

USING A NEGATIVE SUPPLY

Most applications of the AD8305 require only a single supply of

3.0 V to 5.5 V. However, to provide further versatility, dual supplies

may be employed, as illustrated in Figure 37.

BIAS

GENERATOR

VLOG

COMM

VNEG

VSUM

IREF

0.5V

80k

Ω

0.5V

TEMPERATURE

COMPENSATION

6.69kΩ

Q1

COMM

20k

Ω

451

Ω

VREF

VRDZ

14.2k

Ω

Q2

INPT

COMM

2.5V

VPOS

BFIN

SCAL

VOUT

RREF

200k

Ω

1nA

1nF

1k

Ω

1nF

1k

Ω

12k

Ω

5V

10nF

8k

Ω

–

+

+

C1

≤

–

Figure 37. Negative Supply Application

be placed at ground level whenever the input transistor (Q1 in

Figure 33) has a sufficiently negative bias on its emitter. When

default case when VSUM is grounded. This bias does not need

to be accurate, and a poorly defined source can be used. The

source does, however, need to be able to support the quiescent

current as well as the INPT and IREF signal current. For example,

it may be convenient to utilize a forward-biased junction

voltage of about 0.7 V or a Schottky barrier voltage of a little

over 0.5 V. The effect of supply on the dynamic range and

accuracy can be seen in Figure 10.

With the summing node at ground, the AD8305 may now be

used as a voltage-input log amp at either the numerator input,

INPT, or the denominator input, IREF, by inserting a suitably

scaled resistor from the voltage source to the relevant pin. The

overall accuracy for small input voltages is limited by the

voltage offset at the inputs of the JFET op amps.

The use of a negative supply also allows the output to swing below

ground, thereby allowing the intercept to correspond to a midrange

the ACOM pin, and while it does not swing negative for default

operating conditions, it is free to do so, thus, adding a resistor

from VLOG to the negative supply lowers all values of VLOG,

which raises the intercept. The disadvantage of this method is

that the slope is reduced by the shunting of the external resistor,

and the poorly defined ratio of on-chip and off-chip resistances

causes errors in both the slope and the intercept.

BIAS

GENERATOR

VLOG

COMM

VNEG

VSUM

IREF

0.5V

80k

Ω

0.5V

TEMPERATURE

COMPENSATION

6.69kΩ

Q1

COMM

20k

Ω

451Ω

VREF

VRDZ

14.2kΩ

Q2

INPT

COMM

2.5V

VPOS

BFIN

SCAL

VOUT

5V

5V

+ 2

1k

Ω

1nF

1k

Ω

1nF

28.0k

Ω

44.2k

Ω

18nF

REFERENCE

DETECTOR

SIGNAL

DETECTOR

33nF

12.1k

Ω

–

+

Figure 38. Optical Absorbance Measurement