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ADL5304ACPZ-R7 数据表(PDF) 21 Page - Analog Devices

部件名 ADL5304ACPZ-R7
功能描述  High Speed, 200 dB Range, Logarithmic Converter
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5304ACPZ-R7 数据表(HTML) 21 Page - Analog Devices

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Data Sheet
ADL5304
Rev. A | Page 21 of 32
The C1D capacitor effectively reduces the bandwidth of the
denominator input stage. A few picofarads of capacitance
(<5 pF) reduce the bandwidth significantly for currents below
approximately 1 µA, though whereas 1 nF to 10 nF are normally
enough to reduce the bandwidth up to the maximum 10 mA of
input current. When measurement speed is of primary importance,
it is better to add filtering after the FET amp outputs, in which
case, C2D, RD, and C3D are the best locations. The resistor in this
case should not be much larger than 1 kΩ because there is a
bias current that is approximately 35 µA that flows from the
temperature compensation block into each of the VDEN and
VNUM pins. Inserting a resistor, as shown in Figure 48, lifts up
the voltages at the INNM and/or INDN pins and potentially causes
headroom problems in the temperature compensation block.
When IDEN is used as the reference, as is normally done, then it
is recommended that C1D is zero, C2D is a 0.1 µF ceramic
decoupling capacitor, RD is a short, and C3D is not placed.
Adding a capacitor, CFB, adds additional filtering at the buffer
output. This capacitor also helps to optimize the pulse response
by placing a zero across the feedback resistor (2.5 kΩ in the
default configuration). A good value to start with is 22 pF, this
introduces a zero at 2.9 MHz that can improve the pulse responses
for input currents above approximately 100 µA.
Photodiode Bias
The ADL5304 provides for adaptive photodiode bias. A
monitoring transistor, Q3, connected in parallel with Q1 (see
Figure 49), samples 1/10th the input current, INUM. This sampled
current is multiplied by a factor of 11 to give an effective output
current at the IMON pin of 1.1 times INUM. Because the photodiode
produces INUM, the additional current has to flow in an external
resistor, RMNTR, equal to 10 × RS, where RS is the value of the
internal parasitic series resistance of the photodiode. This
ensures that the actual junction of the photodiode is biased as
close as possible to 0 V to minimize dark current. The CMON
capacitor provides potential filtering and dynamic currents
during fast transients. The value for best bias response depends
on the photodiode used and should be determined
experimentally. Nominally, CMON = 0.
If the adaptive bias is not used, the IMON pin must be connected
to ground. It is easy to provide a 0.5 V reverse bias across the
diode by using the 2VLT reference and connecting it to the
cathode. Because the ADL5304 forces the voltage at INUM very
close to 1.500 V, the trimmed 2.000 V ensures a precise 0.5 V
reverse bias for the PD.
MONITOR AND
PD BIAS
(1.1× INUM)
2
3
4
5
6
8
7
30
VSM2
VSM1
RMNTR
32
VSM3
VSM4
IREF
IDEN
INUM
100nA
Q2
Q1
Q3
1.5V
1.5V
9
VDEN
VNUM
IMON
SHIELD
SHIELD
PD
CMON
FROM 1.5V VREF
Figure 49. Adaptive Photodiode Bias
One example of dual-supply operation is shown in Figure 50, where
the 2.000 V (the 2VLT pin) reference ensures a precisely controlled,
reverse bias across the PD. The user can use other reverse bias
voltages but needs to provide them separately. Note that when the
VSMx pins are grounded, the DCBI and INPS pins must also be
grounded.
MONITOR AND
PD BIAS
(1.1× INUM)
2
3
4
5
6
8
7
30
VSM2
VSM1
32
VSM3
VSM4
IREF
IDEN
INUM
100nA
Q2
Q1
Q3
9
VDEN
VNUM
IMON
SHIELD
SHIELD
PD
FROM 2.0V
VREF
Figure 50. PD Bias with VSUM at Ground and Using 2.000 V



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