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ADA4312-1ACPZ-R2 数据表(PDF) 9 Page - Analog Devices |
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ADA4312-1ACPZ-R2 数据表(HTML) 9 Page - Analog Devices |
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9 / 12 page ![]() Data Sheet ADA4312-1 Rev. A | Page 9 of 12 APPLICATIONS INFORMATION ADA4312-1 + – ADA4312-1 – + VCC VCC RL 1:1 RBT RBT RF RG RF CIN CIN RBIAS RBIAS 10k Ω 10k Ω RIADJ 0.1µF 0.1µF 10µF Figure 17. Typical G.hn Application Circuit FEEDBACK RESISTOR SELECTION The feedback resistor value has a direct impact on the closed- loop bandwidth of the current feedback amplifiers used in the architecture of the ADA4312-1 differential line driver. Table 5 provides a guideline for the selection of feedback resistor values used in typical differential line driver circuits (refer to Figure 17). Table 5. Resistor Values and Frequency Performance Gain R F (Ω) R G (Ω) −3 dB SS BW (MHz) 16 V/V 732 97.6 195 12 V/V 750 137 200 8 V/V 768 221 209 4 V/V 806 536 222 Selecting a feedback resistor with a value that is lower than the values in Table 5 can create peaking in the frequency response; in extreme cases, this peaking can lead to instability. Conversely, a feedback resistor that exceeds the values in Table 5 can limit the closed-loop bandwidth. GENERAL OPERATION The ADA4312-1 is a differential line driver designed for single- supply operation in G.hn line driver applications. The core architecture comprises two high speed current feedback amplifiers. The inputs of these amplifiers are arranged in a unique way that facilitates extended differential bandwidth, linearity, and stability while limiting common-mode bandwidth and enhancing common-mode stability. The patented input stage of the core amplifiers is not conducive to operating either core amplifier independently. The ADA4312-1 input stage is designed to operate only in differential applications similar to the circuit shown in Figure 17. HALF-DUPLEX OPERATION In systems such as G.hn PLC modems, half-duplex or time- division duplex (TDD) systems require the line driver to be switched between transmit mode and high output impedance receive mode. The ADA4312-1 is equipped with a shutdown pin (SD, Pin 9) that stops the line driver from transmitting while switching the outputs to a high output impedance equivalent to 10 kΩ in parallel with 2RF + RG (see Figure 17). The shutdown (SD) pin is compatible with standard 3.3 V CMOS logic. If the SD pin is left floating, an internal pull-up resistor places the output in a disabled, high output impedance state. SD logic is referred to GND (Pin 4), which should be connected to 0 V. ESTABLISHING VMID In single-supply applications such as the one shown in Figure 17, it is necessary to establish a midsupply operating point (VMID). To establish VMID, use two 10 kΩ resistors to form a resistor divider from VCC to ground and a 0.1 µF ceramic chip capacitor for decoupling. Place the VMID decoupling capacitor and the RBIAS resistors as close as possible to the ADA4312-1. BIAS CONTROL AND LINEARITY The ADA4312-1 is equipped with a biasing adjustment feature that lowers the quiescent operating current. A resistor (RIADJ) must be placed between IADJ (Pin 5) and GND (Pin 4) for proper operation of the ADA4312-1. Using a resistor larger than 0 Ω reduces the quiescent current of the line driver and improves efficiency in transmit mode. Figure 13 shows the quiescent current vs. RIADJ. |
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