ZL6100ALAF datasheet(14/34 Pages) RENESAS

14 / 34 page

ZL6100

FN6876 Rev 3.00

Page 14 of 34

August 29, 2012

Soft-start Delay and Ramp Times

It may be necessary to set a delay from when an enable signal

is received until the output voltage starts to ramp to its target

value. In addition, the designer may wish to precisely set the

time required for VOUT to ramp to its target value after the

delay period has expired. These features may be used as part

of an overall inrush current management strategy or to

precisely control how fast a load IC is turned on. The ZL6100

gives the system designer several options for precisely and

independently controlling both the delay and ramp time

periods.

The soft-start delay period begins when the EN pin is asserted

and ends when the delay time expires. The soft-start delay

period is set using the DLY (0, 1) pins. Precise ramp delay

timing reduces the delay time variations but is only available

when the appropriate bit in the MISC_CONFIG register has

been set. Please refer to Application Note AN2033 for details.

The soft-start ramp timer enables a precisely controlled ramp

to the nominal VOUT value that begins once the delay period

has expired. The ramp-up is guaranteed monotonic and its

slope may be precisely set using the SS pin.

The soft start delay and ramp times can be set to standard

values according to Tables 7 and 8 respectively.

Note: When the device is set to 0ms or 1ms delay, it will begin its

ramp up after the internal circuitry has initialized (~2ms).

Note: When the device is set to 0ms ramp, it will attempt to

ramp as fast as the external load capacitance and loop settings

will allow. It is generally recommended to set the soft-start

ramp to a value greater than 500µs to prevent inadvertent fault

conditions due to excessive inrush current.

If the desired soft start delay and ramp times are not one of the

values listed in Tables 7 and 8, the times can be set to a

custom value by connecting a resistor from the DLY0 or SS pin

to SGND using the appropriate resistor value from

Table 9. The value of this resistor is measured upon start-up or

Restore and will not change if the resistor is varied after power

has been applied to the ZL6100. See Figure 12 for typical

connections using resistors.

TABLE 6. ZL6100 START-UP SEQUENCE

STEP

STEP NAME

DESCRIPTION

TIME DURATION

Power Applied

Input voltage is applied to the ZL6100’s VDD pin Depends on input supply ramp time

Internal Memory Check

The device will check for values stored in its

internal memory. This step is also performed after

a Restore command.

Approx 5ms to 10ms (device will ignore an

enable signal or PMBus traffic during this period)

Multi-mode Pin Check

The device loads values configured by the multi-

mode pins.

Device Ready

The device is ready to accept an enable signal.

Pre-ramp Delay

The device requires approximately 2ms following

an enable signal and prior to ramping its output.

Additional pre-ramp delay may be configured

using the Delay pins.

Approximately 2ms

TABLE 7. SOFT-START DELAY SETTINGS

DLY0

LOW

(ms)

OPEN

(ms)

HIGH

(ms)

LOW

DLY1

OPEN

510

HIGH

100

200

TABLE 8. SOFT-START RAMP SETTINGS

RAMP TIME

(ms)

LOW

OPEN

HIGH

TABLE 9. DLY AND SS RESISTOR SETTINGS

DLY OR SS

(ms)

RDLY OR RSS

)

DLY OR SS

(ms)

RDLY OR RSS

)

110

28.7

120

31.6

12.1

130

34.8

13.3

140

38.3

14.7

150

42.2

16.2

160

46.4

17.8

170

51.1

19.6

180

56.2

21.5

190

61.9

23.7

200

68.1

100

26.1

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