Data Sheet

AD8264

Rev. B | Page 31 of 40

A DC CONNECTED CONCEPT EXAMPLE

The dc connected concept example in Figure 113 is an application

with the 40-channel AD5381, 3 V, 12-bit DAC. The main difference

between this example and Figure 112 is that, for the same ADR127

1.25 V reference, the full-scale output of the DAC is from 0 V to

2 × VREFIN = 2.5 V. Two options for gain control include the

following:



Use the same circuit as in Figure 112 but use only half the

DAC output voltage from 0 V to 1.25 V. This is the simplest

solution, requiring the fewest extra components. Note that

the overall gain resolution increases by one bit to 11 bits

over the 10-bit AD5314.



Ground GNLO and scale the DAC output so that the

GNHx inputs vary from −0.652 V to +0.625 V. Figure 113

shows a possible circuit implementation using a divider

between the DAC output and a −1.25 V reference.

GNLO cannot simply be increased to 1.25 V because, for a

given supply voltage, GNLO has a limited voltage range to

achieve the full gain span (see Table 5).

However, a third possibility is to use another voltage that is

between 1.2 V and 625 mV on GNLO, such as 1 V. In this case,

the DAC must vary from 0.375 V to 1.625 V to achieve the fully

specified gain range.

Note the gain limits when the differential gain control exceeds

±0.625 V, either to 6 dB or to 30 dB. If the differential gain

control input voltage is exceeded, no gain foldover occurs.

Figure 113 shows how the AD8264 is connected in a PET

application. The PMT generates a negative-going current pulse

that results in a voltage pulse at the preamplifier input and a

differential output pulse on VOLx and VOHx.

To fully appreciate the advantages of the AD8264, note the

common-mode and polarity conversion afforded. The AD9228,

as with most modern ADCs, is a low voltage, single-polarity

device. Recall that the PMT is a high voltage device that yields a

negative pulse. To map the pulse to the input range of the ADC,

the pulse must be inverted, shifted, and amplified to the full

input range of the ADC. This is done by using the gain control,

signal offset, and common-mode features of the AD8264.

The full-scale input of the converter is 0 V to 2 V, with a common-

mode of 1 V. Match the VOCM voltage of the AD8264 to the

ADC common mode (VREF = 1 V), and the two devices can be

connected directly using an appropriate level of the antialiasing

filter. The PMT signal is 0 V to −0.1 V. With a gain of 20× (26 dB),

the AD8264 output signal range is 2 V p-p. Prebias the signal

negative by −0.5 V using the AD8264 OFSx inputs, which sets

VOHx = 1.5 V and VOLx = 0.5 V for VOCM = 1 V. The output

is perfectly matched to the input of the ADC.

Note that, by connecting VOLx to the positive ADC input and

VOHx to the negative ADC input, the negative input pulse is

inverted automatically. The VGAx output is still a negative

pulse, amplified by 20 dB for this example.

+3.3V

–3.3V

0.1µF

NC 6

NC 5

1

2

3

NC

GND

ADR127

REFIN

DAC

AD5314

GND

=

10µF

10µF

1kΩ

1%

1kΩ

1%

1.25V

625mV

GNH1

GNH2

GNH3

GNH4

AD8264

GNLO

EACH

VOCM

VOHx VOLx

ADC

AD9222/

AD9228

VREF

VDD

+1.8V

SENSE

GND

SENSE GROUNDED: VREF = 1V

VNEG

VPOS

IPPx

OFSx

~250nA EACH

VGAx

VGA OUTPUTS TO OTHER

SIGNAL PROCESSING

OUTPUT COMMON-MODE VOLTAGE = 1V

VOHx = 1V, VOLx = 1V; VOFS = 0V

FS = 2V p-p

1µF

0.1µF

0.1µF

+3.3V

+3.3V

Figure 113. Concept Application of AD8264 with 40-Channel AD5381 12-Bit, 3 V DAC and AD9222/AD9228 12-Bit ADC