Data Sheet

ADL5330

Rev. B | Page 19 of 24

CDMA2000 TRANSMIT APPLICATION

To test the compliance to the CDMA2000 base station standard,

an 880 MHz, three-carrier CDMA2000 test model signal (forward

pilot, sync, paging, and six traffic, as per 3GPP2 C.S0010-B,

Table 6.5.2.1) was applied to the ADL5330. A cavity-tuned filter

with a 4.6 MHz pass band was used to reduce noise from the

signal source being applied to the device.

Figure 46 shows the spectrum of the output signal under

channel power ratio is measured in a 30 kHz bandwidth at

750 kHz and 1.98 MHz carrier offset, respectively.

SPAN 15MHz

CENTER 880MHz

1.5MHz/

A

1RM

EXT

–10

–30

–40

–20

–50

–60

–70

–80

–90

–100

–110

1 AVG

1 [T1]

–18.55dBm

880MHz

CH PWR

0.46dBm

ACP Up

–65.13dB

ACP Low

–64.40dB

ALT1 Up

–89.05dB

ALT1 Low

–83.68dB

ALT2 Up

–80.72dB

ALT2 Low

–81.24dB

1

CU3

CU3

CU2

CU2

CU1

CU1

CL1

CL1

CL2

CL2

CL3

CL3

C0

C0

0.4 dB OFFSET

REF LVL

–10dBm

MARKER 1 [T1]

–18.55dBm

880.00000000MHz

RBW 30kHz

VBW 300kHz

SWT 200ms

RF ATT 10dB

MIXER –10dBm

UNIT

dBm

Figure 46. 880 MHz Output Spectrum, Three-Carrier CDMA2000 Test Model

1.98 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter

(Pass Band = 4.6 MHz)

In testing, by holding the gain control voltage steady at 1.4 V,

input power was swept. Figure 47 shows ACPR and noise floor

vs. total output power. Noise floor is measured at 1 MHz

bandwidth at 4 MHz carrier offset.

–90

–0

–10

–20

–30

–40

–50

–60

–70

–80

TOTAL OUTPUT POWER (dBm)

15

–30

–25

–20

–15

–10

–5

0

5

10

–30

–50

–40

–60

–70

–80

–90

–100

–110

–120

NOISE 4MHz OFFSET

ACPR 750kHz OFFSET

ACPR 1.98MHz OFFSET

Figure 47. ACPR vs. Total Output Power, 880 MHz Three-Carrier CDMA2000

750 kHz and 1.98 MHz Carrier Offset

The results show that up to a total output power of +8 dBm,

ACPR remains in compliance with the standard (<−45 dBc at

750 kHz and <−60 dBc at 1.98 MHz). At low output power

levels, ACPR at 1.98 MHz carrier offset degrades as the noise

floor of the ADL5330 becomes the dominant contributor to

measured ACPR. Measured noise at 4 MHz carrier offset begins

to increase sharply above 0 dBm output power. This increase is

not due to noise but results from increased carrier-induced

distortion. As output power drops below 0 dBm total, the noise

floor drops towards −85 dBm.

With a fixed input power of −23 dBm, the output power was

swept from 0 V to 1.4 V. The resulting total output power,

ACPR, and noise floor are shown in Figure 48.

–100

–30

–40

–50

–60

–70

–80

–90

1.4

0

0.2

0.4

0.6

0.8

1.0

1.2

10

0

–10

–20

–30

–40

–50

–60

NOISE 4MHz OFFSET

ACPR 750kHz OFFSET

ACPR 1.98MHz OFFSET

OUTPUT POWER

CDMA2000 Test Model at −23 dBm Total Input Power; ACPR Measured in

30 kHz Bandwidth at 750 kHz and 1.98 MHz Carrier Offset

standard. As the gain control input drops below 1.0 V, the noise

floor drops below −90 dBm.

SOLDERING INFORMATION

On the underside of the chip scale package, there is an exposed

compressed paddle. This paddle is internally connected to the

chip’s ground. Solder the paddle to the low impedance ground

plane on the printed circuit board to ensure specified electrical

performance and to provide thermal relief. It is also recommended

that the ground planes on all layers under the paddle be stitched

together with vias to reduce thermal impedance.