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VS133-R512 数据表(PDF) 4 Page - List of Unclassifed Manufacturers

部件名 VS133-R512
功能描述  Memory Module
PDF  7 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

VS133-R512 数据表(HTML) 4 Page - List of Unclassifed Manufacturers

  VS133-R512 Datasheet HTML 1Page - List of Unclassifed Manufacturers VS133-R512 Datasheet HTML 2Page - List of Unclassifed Manufacturers VS133-R512 Datasheet HTML 3Page - List of Unclassifed Manufacturers VS133-R512 Datasheet HTML 4Page - List of Unclassifed Manufacturers VS133-R512 Datasheet HTML 5Page - List of Unclassifed Manufacturers VS133-R512 Datasheet HTML 6Page - List of Unclassifed Manufacturers VS133-R512 Datasheet HTML 7Page - List of Unclassifed Manufacturers  
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VS133-R512
PDRB-28998-X045-01
Buffalo Technology
(4/7)
5.4 D.C. Characters
Parameter
Symbol
Value
Unit
Test Condition
Operating current
ICC1
MAX 2749 * mA
Burst length=1,
tRC ≥ tRC (min),
IO=0mA,
One bank active
ICC2P
MAX 805 * mA
CKE ≤ VIL(max),
tCK = 12ns
Precharge Standby current in power down mode
ICC2PS
MAX 805 * mA
CKE ≤ VIL(max),
tCK = ∞
ICC2N
MAX 1399 * mA
CKE, /S ≥ VIH(min),
tCK = 12ns
Precharge Standby current in non power down mode
ICC2NS MAX 1039 * mA
CKE ≥ VIH (min),
tCK = ∞
ICC3P
MAX 949 * mA
CKE ≤ VIL(max),
tCK = 12ns
Active standby current in power down mode
ICC3PS
MAX 877 * mA
CKE ≤ VIL(max),
tCK = ∞
ICC3N
MAX 1849 * mA
CKE, /S ≥ VIH(min),
tCK = 12ns
Active standby current in non power down mode
ICC3NS MAX 1309 * mA
CKE ≥ VIH (min),
tCK = ∞
Operating current (Burst mode)
ICC4
MAX 2749 * mA
tCK ≥ tCK (min)
Io=0mA,
One bank active
Auto refresh current
ICC5
MAX 6529 * mA tRC ≥ tRC (min)
Self refresh current
ICC6
MAX 823 * mA CKE ≤ 0.2V
MIN
-10 * µA
Input leakage current
IIL
MAX
10
* µA
All other pins are
not under test=0V
0V ≤ VIN ≤ VCC
Output High Voltage
VOH
MIN
2.4 *
V
IOH = -2mA
Output Low Voltage
VOL
MAX
0.4 *
V
IOL = 2mA
* : No guarantee against this value.
5.5 A.C. Timing Characters
Parameter
Symbol
MIN
MAX
Unit
Clock Period
/CAS Latency = 2
/CAS Latency = 3
tCLK
10
7.5
1000
1000
ns
Clock High Pulse Width
tCH
2.5
——
ns
Clock Low Pulse Width
tCL
2.5
——
ns
Input Setup Time
tSI
1.5
——
ns
Input Hold Time
tHI
0.8
——
ns
Output Valid From Clock
/CAS Latency = 2
/CAS Latency = 3
tAC
——
——
6
5.4
ns
Output Hold From Clock
tOH
2.7
——
ns
/RAS to /CAS Delay
tRCD
20
——
ns
/RAS Active Time
tRAS
45
100,000
ns
/RAS Precharge Time
tRP
20
——
ns
Act to Act Command Period
tRRD
15
——
ns
Row Cycle Time
tRC
67.5
——
ns
Average Periodic Refresh Interval
tREF
——
7.8
µs
Mode Register cycle time
tMRC
15
——
ns



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