VS133-R512

PDRB-28998-X045-01

Buffalo Technology

(5/7)

6. Serial Presence Detect (SPD) Data Structure

Byte

No.

Function

Hex

Value

Function Supported

0

Defines # of bytes written into serial memory at module manufacturer

80

128Bytes

1

Total # of bytes of SPD memory device

08

256Bytes

2

Fundamental memory type (FPM, EDO, SDRAM..)

04

SDR SDRAM

3

# of row addresses on this assembly

0D

13

4

# Column Addresses on this assembly

0A

10

5

# Module Banks on this assembly

02

2Banks

6

Data Width of this assembly

48

7

... Data Width continuation

00

72bits

8

Voltage interface standard of this assembly

01

LVTTL

9

SDRAM Cycle time (highest CAS latency)

75

7.5ns (CL=3)

10

SDRAM Access from Clock (highest CAS latency)

54

5.4ns (CL =3)

11

DIMM Configuration type (non-parity, ECC)

02

ECC

12

Refresh Rate/Type

82

7.8µs

13

Primary SDRAM Width

08

x8bit

14

Error Checking SDRAM width

08

x8bit

15

Minimum Clock Delay

Back to Back Random Column Address

01

1CLK

16

Burst Lengths Supported

8F

Burst Lengths (1,2,4,8,FULL)

17

# of Banks on Each SDRAM Device

04

4Banks

18

CAS# Latency

06

CAS Latency =2,3

19

CS# Latency

01

CS Latency =0

20

Write Latency

01

WE Latency =0

21

SDRAM Module Attributes

1F

Registered with PLL

22

SDRAM Device Attributes: General

0E

Supports Write1/Read Burst

Supports Precharge All

Supports Auto-Precharge

23

SDRAM Cycle time (2nd highest CAS latency)

A0

10ns (CL=2)

24

SDRAM Access from Clock (2nd highest CAS latency)

60

6ns (CL=2)

25

SDRAM Cycle time (3rd highest CAS latency)

00

Non Support

26

SDRAM Access from Clock (3rd highest CAS latency)

00

Non Support

27

Minimum Row Precharge Time

14

20ns

28

Row Activate to Row Activate Min.

0F

15ns

29

RAS to CAS Delay Min

14

20ns

30

Minimum RAS Pulse Width

2D

45ns

31

Density of each bank on module

40

256MB

32

Command and Address signal input setup time

15

1.5ns

33

Command and Address signal input hold time

08

0.8ns

34

Data signal input setup time

15

1.5ns

35

Data signal input hold time

08

0.8ns

36-61 Superset Information (may be used in future)

00

Undefined

62

SPD Data Revision Code

12

Rev 1.2

63

Checksum for bytes 0-62

04

Checksum

64-66

7F

67

83

68-71

Manufacturer’s JEDEC ID code per JEP-108E

00

72

Manufacturing Location

01

MELCO inc.

73-90 Manufacturer’s Part Number

20

Blank

91-92 Revision Code

00

Undefined

93-94 Manufacturing Date

00

Undefined

95-98 Assembly Serial Number

00

Undefined

99-125 Manufacturer Specific Data

00

Undefined

126

Intel specification frequency

64

100MHz Compatible

127

Intel Specification CAS# Latency support

87

Clock=0

CL =2,3

128+ Unused storage locations

00

Undefined