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13

EN29F080

Rev. C, Issue Date: 2001/07/05

the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be

read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the

rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid

after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the

time-out window.

In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2

µs, then

stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all

selected blocks are protected, DQ6 will toggle for about 100

µs. The chip will then return to the read

mode without changing data in all protected blocks.

Toggling either

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is

DQ5 Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase

cycle was not successfully completed.

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the reset command to return the device to reading

array data.

DQ3 Sector Erase Timer

After writing a sector erase command sequence, the output on DQ3 can be used to determine whether or

not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.)

When sector erase starts, DQ3 switches from “0” to “1.” This device does not support multiple sector

erase command sequences so it is not very meaningful. Future devices may support this feature.

DQ2 Erase Toggle Bit

The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle

Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when

the system reads at addresses within those sectors that have been selected for erasure. (The system may

use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era-sure. Thus,

both status bits are required for sector and mode information. Refer to Table 5 to compare outputs for

DQ2 and DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See

also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing

diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.

Typically, a system would note and store the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not