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10

EN29F080

Rev. C, Issue Date: 2001/07/05

The reset command may be written between the sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to reading array data.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to

reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices

codes, and determine whether or not a sector is protected. The Command Definitions table shows the

address and data requirements. This is an alternative method which is intended for PROM programmers

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.

Autoselect mode is then entered and the system may read at any address any number of times, without

needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Byte Programming Command

Programming the EN29F080 is performed on a byte-by-byte basis using a four bus-cycle operation

(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).

When the program command is executed, no additional CPU controls or timings are necessary. An

internal timer terminates the program operation automatically. Address is latched on the falling edge

The program operation is completed when EN29F080 returns the equivalent data to the programmed

location.

bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is

exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the

chip erase command, which in turn invokes the Embedded Erase algorithm. The device does

not require

the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required

to provide any controls or timings during these operations. The Command Definitions table shows the

address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,

the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in

“AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing

waveforms.