AD8432ACPZ-R7 datasheet(25/32 Pages) AD

25 / 32 page

Data Sheet

AD8432

Rev. D | Page 25 of 32

EVALUATION BOARD

Figure 73 is a photo of the AD8432 evaluation board. Completely

assembled and pretested, the board provides convenient and fast

verification of system design and to assess the performance of

the AD8432 under user-specific operating conditions. The

remainder of this section describes the operation and construction

of the board.

Figure 74 through Figure 79 are various artwork and assembly

views and Figure 80 shows the schematic diagram. The board

provides access to the inputs, the outputs, and the gain settings.

As shipped, the board is configured for a gain of 21 dB and 50 Ω

input termination. Multiple combinations of gain and impedance

matching are available to the user.

Figure 73. Evaluation Board

CONNECTION AND OPERATION

Power Supply

The AD8432 requires only a single 5 V supply connected to the

+5V red test loop and black test loop GND next to it. Separate

power pins are provided for the two LNA channels, but the two

amplifier sections are wired together and rf-decoupled by small

inductors as a precaution. The remaining red test loops are for

pin probing as necessary. Should the need for amplifier isolation

arise, simply un-power the unneeded amplifier by removing L3

or L4. (Refer to Figure 74 and Figure 80.

Input Termination

The AD8432 features active input termination and boards are

shipped for 50 Ω. The input impedance is determined by the LNA

gain, and the feedback resistors RFB1 and RFB2 (see the schematic in

Figure 80) and source impedance (refer to the Theory of Operation

section and Table 7). CFB provides the necessary ac coupling

between the input and output when using active termination; a

0.1 μF capacitor is recommended. The RFB and CFB network

presents a load to the OPL; if needed, an equivalent load at OPH

balances the differential output.

Switches CLAMP1 and CLAMP2 connect the input clamping

diodes (IND1 and IND2) across the signal path. The diodes provide

input overvoltage protection in applications where fast transient

pulses exceeding 5.5 V or less than –0.6 V are present. Clamping

diodes enable faster overdrive recovery times, especially at the

lowest gain (12.04 dB). Fast transients are usually not fatal to

the device, which features ESD protection in any event.

Setting the Amplifier Gain

The violet test loops OPnn, GOnn and GMnn and Resistors

R1–R4 and Resistors R9–R12 are provided for gain adjustment.

Install 0 Ω resistors to reduce gain, leaving the positions open to

increase gain. As shipped, the evaluation board is configured for

G = 21 dB (12×). Table 8 lists the configuration for the four

available LNA gain values.

Table 8. Gain Setting Configuration

LNA1

LNA2

GAIN dB(×)

8(4)

18(8)

21(12)

24(16)

open

R10

open

R11

open

R12

open

1 Y = Install 0 Ω.

Output

The 4-pin headers PR1OUT and PR2OUT are placed close to

the AD8432, and provide a way for monitoring the differential

output or the single-ended output using a high impedance

differential probe. The two inner pins of the headers are connected

to OPL/OPH, and the two outer pins of the headers are connected

to ground.

AD8432ACPZ-R7 数据表(PDF) 25 Page - Analog Devices

AD8432ACPZ-R7 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载

链接网址

AD8432ACPZ-R7 数据表(PDF) 25 Page - Analog Devices

AD8432ACPZ-R7 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表 下载

链接网址

数据表下载