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ADL5201ACPZ-R7 数据表(PDF) 17 Page - Analog Devices |
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ADL5201ACPZ-R7 数据表(HTML) 17 Page - Analog Devices |
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17 / 26 page ![]() Data Sheet ADL5201 Rev. C | Page 17 of 26 CIRCUIT DESCRIPTION BASIC STRUCTURE The ADL5201 is a differential variable gain amplifier (VGA) consisting of a 150 Ω digitally controlled passive attenuator followed by a highly linear transconductance amplifier with feedback. ATTENUATOR LOGIC REF VIN+ VIN– VOUT+ VOUT– DIGITAL INPUTS PARALLEL, SPI, FAST ATTACK UP/DOWN ADL5201 gm AMP Figure 52. Simplified Schematic INPUT SYSTEM The dc voltage level at the input of the amplifier is set by an independent internal voltage reference circuit to approximately 1.6 V. The reference is not accessible and cannot be adjusted. The amplifier can be powered down by pulling the PWUP pin low. In power-down mode, the total current is reduced to 7 mA (typical). The dc level at the input remains at approximately 1.6 V, regardless of the state of the PWUP pin. OUTPUT AMPLIFIER Gain of the output amplifier is set to be 22 dB when driving a 150 Ω load. The input and output resistance of this amplifier is set to 150 Ω in matched condition. If the load or the source resistance is not equal to 150 Ω, the following equations can be used to determine the resulting gain and input/output resistances. Voltage Gain = AV = 0.09 × (2000)//RL RIN = (2000 + RL)/(1 + 0.09 × RL) S21 (Gain) = 2 × RIN/(RIN + RS) × AV ROUT = (2000 + RS)/(1 + 0.09 × RS) Note that the at maximum attenuation setting, RS, as seen by the output amplifier, is the output resistance of the attenuator, which is 150 Ω. However, at the minimum attenuation setting, RS is the source resistance that is connected to the input of the part. The dc current to the outputs of each amplifier is supplied through two external chokes. The inductance of the chokes and the resistance of the load, in parallel with the output resistance of the device, add a low frequency pole to the response. The para- sitic capacitance of the chokes adds to the output capacitance of the part. This total capacitance, in parallel with the load and output resistance, sets the high frequency pole of the device. Generally, the larger the inductance of the choke, the higher its parasitic capacitance. Therefore, this trade-off must be considered when the value and type of the choke are selected. For an operation frequency of 15 MHz to 700 MHz driving a 150 Ω load, 1 μH chokes with an SRF of 160 MHz or higher are recommended (such as the 0805LS-102XJBB from Coilcraft). If higher value chokes are used, a 4 MHz zero, due to the internal ac-coupled feedback, causes an increase in S21 of up to 6 dB at frequencies below 4 MHz. The supply current of the amplifier consists of about 35 mA through the VPOS pin and 50 mA through the two chokes combined. The latter increases with temperature at approximately 2.5 mA per 10°C. The total choke current increases to 75 mA for high performance mode. The amplifier has two output pins for each polarity, and they are oriented in an alternating fashion. When designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. To minimize the parasitic capacitance, a good practice is to avoid any ground or power plane under this routing region and under the chokes. GAIN CONTROL The gain can be adjusted using the parallel control interface, the serial peripheral interface, or the gain up/down interface. In general, the gain step size is 0.5 dB, but larger sizes can be programmed using the various interfaces, as described in the Digital Interface Overview section. The amplifier has a maximum gain of +20 dB (Code 0) to −11.5 dB (Code 63). The noise figure of the amplifier is approximately 7.5 dB at the maximum gain setting, and it increases as the gain is reduced. The increase in noise figure is equal to the reduction in gain. The linearity of the part, measured at the output, is first-order independent of the gain setting. From −4 dB to +20 dB gain, the OIP3 is approximately 50 dBm into a 150 Ω load at 200 MHz (0 dBm per tone). At gain settings below −4 dB, the OIP3 drops to approximately 40 dBm. |
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