ADL5201ACPZ-R7 datasheet(18/26 Pages) AD

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ADL5201

Data Sheet

Rev. C | Page 18 of 26

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 53 shows the basic connections for operating the ADL5201.

A voltage between 4.5 V and 5.5 V should be applied to the

VPOS pins. Each supply pin should be decoupled with at least

one low inductance, surface-mount ceramic capacitor of 0.1 μF,

placed as close as possible to the device.

The outputs of the ADL5201 must be pulled up to the positive

supply with 1 μH RF chokes. The differential outputs are biased

to the positive supply and require ac coupling capacitors, preferably

0.1 μF. Similarly, the input pins are at bias voltages of about 1.6 V

above ground and should be ac-coupled, as well. The ac coupling

capacitors and the RF chokes are the principle limitations for

operation at low frequencies.

The digital pins (mode control pins, associated SPI and parallel

gain control pins, PM, and PWUP) operate on a voltage of 3.3 V.

To enable the ADL5201, the PWUP pin must be pulled high

(1.4 V ≤ PWUP ≤ 3.3 V). Taking PWUP low puts the ADL5201

in sleep mode, reducing current consumption to approximately

7 mA at ambient temperature.

ADC DRIVING

The ADL5201 is a highly linear, variable gain amplifier that

is optimized for ADC interfacing. The output IMDs and noise

floor remain constant throughout the 31.5 dB gain range. This

is a valuable feature in a variable gain receiver, where it is

desirable to maintain a constant instantaneous dynamic range

as the receiver range is modified. The output noise is 15 nV/√Hz,

which is compatible with 14- or 16-bit ADCs. The two-tone

IMDs are usually greater than −100 dB for −1 dBm into 150 Ω

or 2 V p-p output. The 150 Ω output impedance makes the task

of designing a filter for the high input impedance ADCs more

straightforward.

GAIN CONTROL INTERFACE

0.1µF

BALANCED

SOURCE

BALANCED

LOAD

1µH

0.1µF

10µF

+VPOS

MODE0

ADL5201

3.3V

GAIN MODE INTERFACE

MODE0

MODE1

GND

VIN–

VIN+

GND

LATCH

VOUT+

VOUT–

VOUT+

VOUT–

VPOS

Figure 53. Basic Connections

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