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ADL5336ACPZ-R7 数据表(PDF) 4 Page - Analog Devices

部件名 ADL5336ACPZ-R7
功能描述  Cascadable IF VGAs with Programmable RMS Detectors
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5336ACPZ-R7 数据表(HTML) 4 Page - Analog Devices

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ADL5336
Data Sheet
Rev. C | Page 4 of 30
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
f = 350 MHz
Noise Figure
VGA1, Gain Code 00, VGAIN = 1 V
8
dB
VGA2, Gain Code 11, VGAIN = 1 V
7.7
dB
Output IP3
VGA1, Gain Code 00, VGAIN = 1 V
12 (19)
dBV (dBm)
OutputVoltage Level of 1.0 V p-p
VGA1, Gain Code 11, VGAIN = 1 V
10.5 (17.5)
dBV (dBm)
VGA2, Gain Code 00, VGAIN = 1 V
18 (28)
dBV (dBm)
VGA2, Gain Code 11, VGAIN = 1 V
16 (26)
dBV (dBm)
Output P1dB
VGA1, Gain Code 00, VGAIN = 1 V
0 (7)
dBV (dBm)
VGA1, Gain Code 11, VGAIN = 1 V
0 (7)
dBV (dBm)
VGA2, Gain Code 00, VGAIN = 1 V
−1.5 (+8.5)
dBV (dBm)
VGA2, Gain Code 11, VGAIN = 1 V
−1.5 (+8.5)
dBV (dBm)
SQUARE LAW DETECTORS
DTO1, DTO2
Output Setpoint
SPI controlled, 3 dB steps
−24
−3
dBV
Output Range
0.1
VS/2
V
AGC Step Response Range
5 dB input step, CAGC = 0.1 µF
1.5
ms
DIGITAL LOGIC
LE, CLK, DATA, SDO
Input High Voltage, VINH
>2.2
V
Input Low Voltage, VINL
<1.8
V
Input Current, IINH/IINL
<1
µA
Input Capacitance, CIN
2
pF
SPI TIMING
LE, CLK, DATA, SDO
fCLK
20
MHz
tDH
DATA hold time
5
ns
tDS
DATA setup time
5
ns
tLH
LE hold time
5
ns
tLS
LE setup time
5
ns
tPW
CLK high pulse width
5
ns
tD
CLK-to-SDO delay
5
ns
POWER AND ENABLE
VPOS, VPSD, COM, COMD, ENBL
Supply Voltage Range
4.5
5
5.5
V
Total Supply Current
ENBL = 5 V
80
mA
Disable Current
ENBL = 0 V
4
mA
Disable Threshold
2.3
V
Enable Response Time
Delay following low-to-high transition until
device meets full specifications in VGA mode
800
ns
Disable Response Time
Delay following high-to-low transition until
device produces full attenuation in VGA mode
20
ns



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