Data Sheet

AD8143

Rev. A | Page 21 of 24

Typically, the input signals are received over 100 Ω differential

transmission lines. A 100 Ω differential transmission line is

readily realized on the printed circuit board using two well-

matched, closely-spaced 50 Ω single-ended traces that are

coupled through the ground plane. The traces that carry the

single-ended output signals are most often 75 Ω for video

signals. Output signal connections should include series

termination resistors that are matched to the impedance

of the line they are driving.

Broadband power supply decoupling networks should be placed

as close as possible to the supply pins. Small surface-mount

ceramic capacitors are recommended for these networks, and

tantalum capacitors are recommended for bulk supply

decoupling.

Minimizing Parasitic Reactances in the Feedback Network

Parasitic trace capacitance and inductance are both reduced

when the traces that connect the feedback network together are

reduced in length. Removing the copper from all planes below

the traces reduces trace capacitance, but increases trace inductance

because the loop area formed by the trace and ground plane is

increased. A reasonable compromise that works well is to void

all copper directly under the feedback loop traces and component

pads with margins on each side approximately equal to one

trace width. Combining this technique with minimizing trace

lengths is effective in keeping parasitic trace reactances in the

feedback loop to a minimum. Additionally, all components used

in the feedback network should be in 0402 surface-mount

packages. Figure 45 illustrates the magnified view of a proven

feedback network layout that provides excellent performance. Note

that the internal layers are not shown.

It is strongly recommended that the layout shown in Figure 45,

or something very similar, be used for the three AD8143

feedback networks.

A conservative estimate for feedback-loop trace capacitance in

each loop of the layout shown in Figure 45 is 2 pF. This value is

viewed as the minimum load capacitance and is reflected in the

frequency response and transient response plots.

Maximizing Heat Removal

The AD8143 pinout includes ground connections on its corner

pins to facilitate heat removal. These pins should be connected

to the exposed paddle on the underside of the AD8143 and to a

ground plane on the component side of the board. Additionally,

a 5 × 5 array of thermal vias connecting the exposed pad to

internal ground planes should be placed inside the PCB pad

that is soldered to the exposed pad. Using these techniques

is highly recommended in all applications, and is required in

±12 V applications where power dissipation is the greatest.

Figure 45 illustrates how to optimize the circuit board layout

for heat removal.

Designs must often conform to design-for-manufacturing

(DFM) rules that stipulate how to lay out PCBs in such a way

as to facilitate the manufacturing process. Some of these rules

require thermal relief on pads that connect to planes, and the

rules may preclude the use of the technique illustrated in Figure 45.

In these cases, the ground pins should be connected to the exposed

paddle and component-side ground plane using techniques that

conform to the DFM requirements.

GND

GND

GND

GND

GND

GND

GND

= CIRCUIT SIDE

= COMPONENT SIDE

Figure 45. Recommended Layout for Feedback Loops and Grounding