ADCMP606/ADCMP607

Data Sheet

Rev. C | Page 14 of 14

OUTLINE DIMENSIONS

1.30 BSC

COMPLIANT TO JEDEC STANDARDS MO-203-AB

1.00

0.90

0.70

0.46

0.36

0.26

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

0.10 MAX

1.10

0.80

0.40

0.10

0.22

0.08

3

1

2

4

6

5

0.65 BSC

COPLANARITY

0.10

SEATING

PLANE

0.30

0.15

Figure 26. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

1.65

1.50 SQ

1.35

0.50

0.40

0.30

1

0.50

BSC

BOTTOM VIEW

TOP VIEW

12

4

6

7

9

10

3

EXPOSED

PAD

PIN 1

INDICATOR

3.10

3.00 SQ

2.90

SEATING

PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

0.30

0.23

0.18

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.80

0.75

0.70

Figure 27. 12-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm and 0.75 mm Package Height

(CP-12-5)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature Range

Package Description

Package

Option

Branding

ADCMP606BKSZ-R2

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package [SC70]

KS-6

G0S

ADCMP606BKSZ-REEL7

−40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor Package [SC70]

KS-6

G0S

EVAL-ADCMP606BKSZ

Evaluation Board

ADCMP607BCPZ-R2

−40°C to +125°C

12-Lead Lead Frame Chip Scale Package [LFCSP]

CP-12-5

G0H

ADCMP607BCPZ-R7

−40°C to +125°C

12-Lead Lead Frame Chip Scale Package [LFCSP]

CP-12-5

G0H

ADCMP607BCPZ-WP

−40°C to +125°C

12-Lead Lead Frame Chip Scale Package [LFCSP]

CP-12-5

G0H

EVAL-ADCMP607BCPZ

Evaluation Board

1

Z = RoHS Compliant Part.

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D05917-0-4/16(C)