LTC6752ISC6-1 datasheet(9/30 Pages) AD

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LTC6752/LTC6752-1/

LTC6752-2/LTC6752-3/

LTC6752-4

6752fc

For more information www.linear.com/LTC6752

elecTrical characTerisTics (V

CC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3 only).

The l denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C.

LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Latching/Adjustable Hysteresis Characteristics (LTC6752-2/LTC6752-3 Only)

VLE/HYST

LE/HYST Pin Voltage

Open Circuit

1.05

1.25

1.45

RHYST

Resistance Looking Into LE/HYST

LE/HYST Pin Voltage < Open Circuit Value

kΩ

VHYST_LARGE Modified Input Hysteresis Voltage (Note 2)

VLE/HYST = 800mV

VIL_LE

Latch Pin Voltage, Latch Guaranteed

0.3

VIH_LE

Latch Pin Voltage, Hysteresis Disabled

Output Not Latched

1.7

IIH_LE

Latch Pin Current High

VLE/HYST = 1.7V

µA

IIL_LE

Latch Pin Current Low

VLE/HYST = 0.3V

–70

–47

µA

tSETUP

Latch Setup Time (Note 10)

–2

tHOLD

Latch Hold Time (Note 10)

tPL

Latch To Output Delay

Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)

ISD_VCC

Shutdown Mode Input Stage Supply Current VSHDN = 0.6V

500

650

750

µA

ISD_VDD

Shutdown Mode Output Stage Supply

Current

VSHDN = 0.6V, LTC6752-2

170

400

450

µA

VSHDN = 0.6V, LTC6752-3

240

600

650

µA

tSD

Shutdown Time

Output Hi-Z

VIH_SD

Shutdown Pin Voltage High

Part Guaranteed to Be Powered On

1.3

VIL_SD

Shutdown Pin Voltage Low

Part Guaranteed to Be Powered Off

0.6

tWAKEUP

Wake-Up Time from Shutdown

VOD = 100mV, Output Valid

100

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Reverse biased ESD protection diodes exist on all input,

shutdown, latching/hysteresis and output pins. If the voltage on these

pins goes 300mV beyond either supply rail, the current should be limited

to less than 10mA. This parameter is guaranteed to meet specification

through design and/or characterization. It is not production tested.

Note 3: A heat sink may be required to keep the junction temperature

below the absolute maximum rating. This parameter is guaranteed to meet

specified performance through design and/or characterization. It is not

production tested.

Note 4: The LTC6752I/LTC6752-1I/LTC6752-2I/LTC6752-3I/LTC6752-4I

are guaranteed to meet specified performance from –40°C to 85°C. The

LTC6752H/LTC6752-1H/LTC6752-2H/LTC6752-3H/LTC6752-4H are

guaranteed to meet specified performance from –40°C to 125°C.

Note 5: Total output supply voltage range is guaranteed by the PSRR_VDD

test. Total input supply voltage range for the LTC6752-2, LTC6752-3 and

LTC6752-4 is guaranteed by the PSRR_VCC test. For the LTC6752 and

LTC6752-1, the supply voltage range is guaranteed by the PSRR_VCC test.

The LTC6752MP is guaranteed to meet specified performance from –55°C

to 125°C.

Note 6: Both hysteresis and offset are measured by determining positive

and negative trip points (input values needed to change the output in the

opposite direction). Hysteresis is defined as the difference of the two trip

points and offset as the average of the two trip points.

Note 7: Guaranteed by CMRR test.

Note 8: Propagation delays are measured with a step size of 150mV.

Note 9: Propagation delay skew is defined as the difference of the

propagation delays for positive and negative steps for the LTC6752,

LTC6752-1, LTC6752-2 and LTC6752-4, and the difference in propagation

delays between the complementary outputs for the LTC6752-3.

Note 10: Latch setup time is defined as the minimum time before the

LE/HYST pin is asserted low for an input signal change to be acquired and

held at the output. Latch hold time is defined as the minimum time before

an input signal change for a high to low transition on the LE/HYST pin to

prevent the output from changing. See Figure 7 for a graphical definition of

these terms.

Note 11: Toggling is defined to be valid if the output swings as follows:

from 10% of VDD - VEE to 90% of VDD - VEE for the LTC6752-2/

LTC6752-3/LTC6752-4, and from 10% of VCC - VEE to 90% of VCC - VEE

for the LTC6752/LTC6752-1. It is tested with a 1kΩ load to VCM

Note 12: The devices have effectively infinite gain when hysteresis is

enabled.

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