ADCMP396ARZ datasheet(13/18 Pages) AD

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Data Sheet

ADCMP394/ADCMP395/ADCMP396

Rev. B | Page 13 of 18

WINDOW COMPARATOR FOR NEGATIVE

VOLTAGE MONITORING

Figure 35 shows the circuit configuration for negative supply

voltage monitoring. To monitor a negative voltage, a reference

voltage is required to connect to the end node of the voltage

divider circuit, in this case, REF.

Figure 35. Negative Undervoltage/Overvoltage Monitoring Configuration

Equation 7, Equation 9, and Equation 10 need some minor

modifications. The reference voltage, VREF, is added to the

overall voltage drop; therefore, it must be subtracted from VM,

VUV, and VOV before using each of them in Equation 7, Equation 9,

and Equation 10.

To monitor a negative voltage level, the resistor divider circuit

divides the voltage differential level between VREF and the

negative supply voltage into the high-side voltage, VNH, and the

low-side voltage, VNL. The high-side voltage, VNH, is connected

to INA+, and the low-side voltage, VNL, is connected to INB−.

To trigger an overvoltage condition, the monitored voltage must

exceed the nominal voltage in terms of magnitude, and the

high-side voltage (in this case, VNH) on the INA+ pin must be

more negative than ground. Calculate the high-side voltage,

VNH, by using the following formula:



REF

GND

































(11)

In addition,





REF







(12)

Therefore, RZ, which sets the desired trip point for the

overvoltage monitor, is calculated by







REF





(13)

To trigger an undervoltage condition, the monitored voltage

must be less than the nominal voltage in terms of magnitude,

and the low-side voltage (in this case, VNL) on the INB− pin

must be more positive than ground. Calculate the low-side

voltage, VNL, by the following:



REF

GND

































(14)

Because RZ is already known, RY can be expressed as follows:







REF





(15)

When RY and RZ are known, RX is then calculated by





REF





(16)

PROGRAMMABLE SEQUENCING CONTROL CIRCUIT

The circuit shown in Figure 36 is used to control power supply

sequencing. The delay is set by the combination of the pull-up

resistor (RPULLUP), the load capacitor (CL), and the resistor

divider network.

Figure 36. Programmable Sequencing Control Circuit

Figure 37 shows a simple block diagram for a programmable

sequencing control circuit. The application delays the enable signal,

EN, of the external regulators (LDO x) in a linear order when

the open-drain signal (SEQ) changes from low to high impedance.

The ADCMP394/ADCMP395/ADCMP396 have a defined output

state during startup, which prevents any regulator from turning

on if VCC is still below the UVLO threshold.

Figure 37. Simplified Block Diagram of a Programmable

Sequencing Control Circuit

OUTA

INA+

REF

INA–

OUTB

INB+

INB–

VNL

VNH

OUTA

OUTB

OUTC

OUTD

RPULL-UP

VREF/VCC

SEQ

INA+

INA–

INB+

INB–

INC+

INC–

IND+

IND–

OUT

GND

LDO 1

3.0V

3.3V

OUT

GND

LDO 2

1.8V

OUT

GND

LDO 3

2.5V

OUT

GND

LDO 4

1.2V

GND

VREF/VCC

SEQ

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