ADCMP396ARZ datasheet(15/18 Pages) AD

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Data Sheet

ADCMP394/ADCMP395/ADCMP396

Rev. B | Page 15 of 18

Figure 40. Mirrored Voltage Sequencer Timing Diagram

The timing diagram for the mirrored voltage sequencer is

shown in Figure 40.

Equation 18 through Equation 21 must account for the additional

resistance, RMIRROR, in the calculations of the voltage thresholds.

To calculate these new thresholds, see Equation 28 through

Equation 31.























MIRROR

PULLUP

REF

(28)























MIRROR

PULLUP

REF

(29)























MIRROR

PULLUP

REF

(30)























MIRROR

PULLUP

REF

(31)

RMIRROR provides the mirrored delay by prolonging the discharge

time of the capacitor. The mirrored voltage sequencer uses the

same threshold in Equation 28 to Equation 31 in a decreasing

order. To calculate the exact value of the mirrored delay time,

see Equation 32 through Equation 35.

















REF

MIRROR

(32)

















REF

MIRROR

(33)

















REF

MIRROR

(34)

















REF

MIRROR

(35)

MIRRORED VOLTAGE SEQUENCER EXAMPLE

To illustrate how the mirrored voltage sequencer works, see

Figure 37 and then consider a system that uses a VREF of 1 V and

requires a delay of 50 ms when SEQ changes from low to high

impedance, and between each regulator when turning on. These

considerations require a rise time of at least 200 ms for the pull-up

resistor (RPULLUP) and the load capacitor (CL). The sum of the

resistance of RMIRROR and RPULLUP must be large enough to charge the

capacitor longer than the minimum required delay. For a

symmetrical mirrored power-down sequence, the value of RMIRROR

must be much larger than RPULLUP. A 10 kΩ RPULLUP value limits the

pull-down current to 100 μA while giving a reasonable value for

RMIRROR. A typical 1 μF capacitor together with a 150 kΩ RMIRROR

value gives a value of

tMAX = 2.2((160 × 103) × (1 × 10−6)) = 351 ms

(36)

The threshold voltage required by each comparator is set by

Equation 28 to Equation 31. For example,



























160

REF 1

where V1 = 268.38 mV.

Therefore, V2 = 464.74 mV, V3 = 608.39 mV, and V4 =

713.5 mV.

Next, consider 10 μA as the maximum current (IDIV) flowing

through the resistor divider network. This current gives the total

resistance of the divider network (RDIV) and the individual

resistor values using Equation 22 to Equation 27, resulting in

the following:



RDIV = 100 kΩ



R1 = 26.84 kΩ ≈ 26.7 kΩ



R2 = 19.64 kΩ ≈ 19.6 kΩ



R3 = 14.37 kΩ ≈ 14.3 kΩ



R4 = 10.51 kΩ ≈ 10.5 kΩ



R5 = 28.65 kΩ ≈ 28.7 kΩ

SEQ

VCL

OUT4

OUT3

OUT2

OUT1

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