SCAN182245ESSMQB datasheet(4/18 Pages) NSC

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Description of BOUNDARY-SCAN Circuitry

The scan cells used in the BOUNDARY-SCAN register are

one of the following two types depending upon their loca-

tion Scan cell TYPE1 is intended to solely observe system

data while TYPE2 has the additional ability to control sys-

tem data (See IEEE Standard 11491

Figure 10-11 for a

further description of scan cell TYPE1 and

Figure 10-12 for

a further description of scan cell TYPE2)

Scan cell TYPE1 is located on each system input pin while

scan cell TYPE2 is located at each system output pin as

well as at each of the two internal active-high output enable

signals AOE controls the activity of the A-outputs while

BOE controls the activity of the B-outputs Each will activate

their respective outputs by loading a logic high

The BYPASS register is a single bit shift register stage iden-

tical to scan cell TYPE1 It captures a fixed logic low

Bypass Register Scan Chain Definition

Logic 0

TLF11657 – 17

SCAN182245A Product IDCODE

(32-Bit Code per IEEE 11491)

Version Entity

Part

Manufacturer Required by

Number

11491

0000

111111 0000000000 00000001111

MSB

LSB

The INSTRUCTION register is an 8-bit register which cap-

tures the default value of 10000001 (SAMPLEPRELOAD)

during the CAPTURE-IR instruction command The benefit

of capturing SAMPLEPRELOAD as the default instruction

during CAPTURE-IR is that the user is no longer required to

shift in the 8-bit instruction for SAMPLEPRELOAD The se-

quence of CAPTURE-IR

x EXIT1-IR x UPDATE-IR

will update the SAMPLEPRELOAD instruction For more

information refer to the section on instruction definitions

Instruction Register Scan Chain Definition

TLF11657 – 10

MSB

x LSB

Instruction Code

Instruction

00000000

EXTEST

10000001

SAMPLEPRELOAD

10000010

CLAMP

00000011

HIGH-Z

01000001

SAMPLE-IN

01000010

SAMPLE-OUT

00100010

EXTEST-OUT

10101010

IDCODE

11111111

BYPASS

All Others

BYPASS

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