2–5

Table 2–4. Hardware Selection of Serial Audio Modes

MODE

MOD2 PIN

MOD1 PIN

MOD0 PIN

SERIAL INTERFACE

SDIN

0

0

0

0

16 bit, MSB first; right justified

1

0

0

1

20 bit, MSB first; right justified

2

0

1

0

24 bit, MSB first; right justified

3

0

1

1

16 bit IIS

4

1

0

0

20 bit IIS

5

1

0

1

24 bit IIS

6

1

1

0

16 bit MSB first, left justified

7

1

1

1

16 bit DSP frame

The following figures illustrate the relationship between the SCLK, LRCLK and the serial data I/O for the different

interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0.

2.8.1

MSB First Right Justified (for 16-, 20-, 24-bits)

X

MSB

LSB

X

MSB

LSB

SCLK

LRCLK = Fs

SDIN

Left Channel

Right Channel

Figure 2–6. MSB First Right Justified

Note the following characteristics of this protocol.

•

Left channel is received when LRCLK is high.

•

Right channel is received when LRCLK is low.

•

The SDIN data is justified to the trailing edge of the LRCLK

•

SDIN is sampled at the rising edge of SCLK.

•

If LRCLK phase changes by more than 10 MCLKs, then the chip automatically resets.

2.8.2

IIS Compatible Serial Format ( for 16-, 20-, 24-bits)

X

MSB

LSB

X

MSB

LSB

SCLK

LRCLK = Fs

SDIN

Left Channel

Right Channel

Figure 2–7. IIS Compatible Serial Format

Note the following characteristics of this protocol.