4–2

tw(FSHIGH)

64 fs

16-Bit Left Channel Data

16-Bit Left Channel Data

16-Bit Left Channel Data

32-Bit Ignore

SCLK

LRCLK

SDIN

Figure 4–5. DSP Serial Port Expanded Timing

tsu(SDIN) = 20 ns

th(SDIN) = 10 ns

SCLK

SDIN

NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns)

Figure 4–6. DSP Absolute Timing Requirement