TPS54980

SLVS452A − FEBRUARY 2003 − REVISED FEBRUARY 2005

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12

PERFORMANCE GRAPHS

Figure 12

50

55

60

65

70

75

80

85

90

95

100

0

246

8

10

IO − Output Current − A

EFFICIENCY

vs

OUTPUT CURRENT

VI = 3.3 V

Figure 13

1.79

1.792

1.794

1.796

1.798

1.8

1.802

1.804

1.806

1.808

1.81

02

4

6

8

10

IO − Output Current − A

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

VI = 3.3 V

Figure 14

1.79

1.792

1.794

1.796

1.798

1.8

1.802

1.804

1.806

1.808

1.81

3

3.25

3.5

3.75

4

IO = 9 A

IO = 4.5 A

IO = 0 A

VI − Input Voltage − V

OUTPUT VOLTAGE

vs

INPUT VOLTAGE

Figure 15

−60

−50

−40

−30

−20

−10

0

10

20

30

40

50

60

−180

−150

−120

−90

−60

−30

0

30

60

90

120

150

180

Phase

Gain

f − Frequency − Hz

LOOP RESPONSE

VI = 5 V,

IO = 0 A,

fS = 700 kHz

100

1 k

10 k

100 k

1 M

Figure 16

25

35

45

55

65

75

85

95

105

115

125

AMBIENT TEMPERATURE

vs

LOAD CURRENT(1)

IO − Output Current − A

02468

10

12

14

16

fs = 700 kHz,

TJ = 125°C,

VI = 3.3 V,

VO = 1.8 V

Figure 17

OUTPUT AND INPUT RIPPLE

t − Time − 1

µs/div

Figure 18

LOAD TRANSIENT RESPONSE

t − Time −100

µs/div

I = 2.25 A to 6.75 A

Figure 19

START-UP TIMING

t − Time −1 ms/div

VIO

V(core)

PWRGD(I/O)

PWRGD(CORE)

Figure 20

POWER DOWN TIMING

t − Time −100 ms/div

VIO

V(core)

PWRGD(I/O)

PWRGD(CORE)

(1) Safe operating area is applicable to the test board conditions in the Dissipation Ratings