MP7643

6

Rev. 1.00

Figure 1. Timing Diagram

1/2 LSB

1/2 LSB

A1, A0

DB0 to DB7

LD

2-4

Decoder

A0, A1

LD

To DAC1 Latch Enable

To DAC2 Latch Enable

To DAC3 Latch Enable

To DAC4 Latch Enable

Figure 2. Input Control Logic (Simplified)

Block Diagram

L

L

L

DAC1 Transparent

↑

L

L

DAC1 Latched

L

L

H

DAC2 Transparent

↑

L

H

DAC2 Latched

L

H

L

DAC3 Transparent

↑

H

L

DAC3 Latched

L

H

H

DAC4 Transparent

↑

H

H

DAC4 Latched

H

X

X

No Operation

LD

A1

A0

Operation

Table 1. Truth Table

D7

D6

D5

D4

D3

D2

D1

D0

MSB

LSB

DAC Output Voltage

)

D

256

0000

0

0

00

(

1

)

256

1111

1

1

10

1111

1

1

11

000

Table 2. DAC Transfer Function

00

00

1

()

256

()

256

255

254

Note: These outputs must be ratioed up for gain in the output amplifier.