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L9848

logic circuitry and other miscellaneous functions. Notice that if the L9848 is interfaced to a processor operating

with a lower voltage (e.g. 3.0 VDC), the microprocessor inputs connected to the L9848 will swing from 0 to 5.0

VDC.

Discrete Inputs (IN5-6)

These inputs allow Output5-6 to be enabled via this external pin without the use of the SPI. A logic "1" on these

inputs enables the corresponding output no matter what the status of the SPI command register. A logic "0" on

these inputs disables the corresponding output if the SPI command register is not commanding this output on.

These pins can be left "open" if the outputs are controlled only via the SPI (internally pulled down). These inputs

are ideally suited for non-inductive loads that are pulse width modulated (PWMed). This allows PWM control

without the use of the SPI. The TTL level compatible input voltages allow proper operation with microprocessors

that are using 5.0V or 3.0V for their Vdd supply.

Serial Peripheral Interface (SPI)

A standard serial peripheral interface, consisting of Serial Clock (SCLK), Data Out (DO), Data In (DI), and Chip

Select (CS) is implemented to allow access to the internal registers of the L9848. All outputs are controlled via

the SPI.The input pins CS, SCLK, and DI have TTL level compatible input voltages allowing proper operation

from microprocessors that are using 5.0V or 3.0V for their VDD supply. The design of the L9848 allows a "daisy-

chaining" of multiple L9848's to further reduce the need for controller pins.

– Serial Data Output (DO)

This output pin is in a tri-state condition when CS is a logic "0" (LOW). When CS is a logic "1" (HIGH),

this pin always transmits 8bits of data from the fault register to the digital controller. After the first 8bits

data are transmitted the DO output then sequentially transmits the digital data that was just received

(8 SCLK cycles earlier) on the DI pin. The DO output continues to transmit the 8 SCLK delayed bit

data from the DI input until CS eventually transitions from a logic "1" to a logic "0". DO data changes

state 10 ns or later, after the falling edge of SCLK. By definition, the MSB (Table 3) is the first bit of

the byte transmitted on DO and the LSB is the last bit of the byte transmitted on DO, once CS tran-

sitions from a logic "0" to a logic "1".

– Serial Data Input (DI)

This input takes data from the digital controller while CS is HIGH. The L9848 accepts an 8bit data

stream to command the outputs ON or OFF. By definition, the MSB (Table 1) is the first bit of each

byte received on DI and the LSB is the last bit of each byte received on DI, once CS transitions from

a logic "0" to a logic "1".

– Chip Select (CS)

This is the chip select input pin. On the rising edge of CS, the DO pin switches from tri-state to active-

out mode. While CS is high, register data is shifted in and shifted out by the DI and DO pin, respec-

tively, on each subsequent SCLK. On the falling edge of CS, the DO pin switches back to tri-state

mode and the fault register will be "Cleared" if a valid DI byte was received.

A valid DI byte is defined as such:

1st

A multiple of 8 bits was received

2nd

SCLK was low when CS went low

3rd

Current SPI cycle started when SCLK was low

The fault data is not cleared unless all of the 3 previous conditions have been met. A SCLK transition

must be seen before CS is interpreted as active. To allow sufficient time to reload the fault registers,

the CS pin must remain low for a minimum of 1µs prior to going high again, before it starts shifting