Micrel

MICRF009

January 18, 2005

10

M9999-011805

(408) 955-1690

Step 5: Selecting The Demodulator Filter

Bandwidth

The input SEL0 controls the demodulator filter bandwidth in

two binary steps, (625Hz to 1250Hz in sweep, 1250Hz to

2500Hz in fixed mode), see Table 3. Bandwidth must be

selected according to the application. The demodulator

bandwidth should be set according to equation 8. SEL1

tied to VSS by default.

Demodulator Bandwidth

=

0.65

shortest pulse - width

(8)

It should be noted that the values indicated in Table 1 are

the nominal values. The filter bandwidth scales linearly with

frequency so the exact value will depend on the operating

frequency. Refer to the “Electrical Characteristics” for the

exact filter bandwidth at a chosen frequency.

Demodulator Bandwidth

SEL0

Sweep Mode

Fixed Mode

1

1250Hz

2500Hz

0

625Hz

1250Hz

Table 3. Nominal Demodulator Filter Bandwidth

vs. SEL0 and Operating Mode at 433.92MHz

Power Supply Bypass Capacitors

Supply bypass capacitors are strongly recommended.

They should be connected to VDDBB and VDDRF and

should have the shortest possible lead lengths. For best

performance, connect VSSRF to VSSBB, VDDBB to

VDDRF at the power supply only (that is, keep base-band

currents from flowing through the RF return path).

Increasing Selectivity with Optional Bandpass Filter

For

applications

located

in

high

ambient

noise

environments, a fixed value band-pass network may be

connected between the ANT pin and VSSRF to provide

additional receiver selectivity and input overload protection.

A minimum input configuration is included in Figure 9. It

provides some filtering and necessary overload protection.

Data Squelching

During quiet periods (no signal), the data output (DO pin)

transitions randomly with noise. Most decoders can

discriminate between this random noise and actual data.

For some systems, it does present a problem. There are

three possible approaches to reduce this output noise:

1. Analog squelch to raise the demodulator threshold.

2. Digital squelch to disable the output when data is not

present.

3. Output filter to filter the (high frequency) noise

glitches on the data output pin.

The simplest solution is to add analog squelch by

introducing a small offset, or squelch voltage, on the CTH

pin so that noise does not trigger the internal comparator.

Usually 20mV to 30mV is sufficient, and may be achieved

by connecting a several-meg-ohm resistor from the CTH

pin to either VSSBB or VDDBB, depending on the desired

offset polarity. Since MICRF009’s receiver AGC noise at

the internal comparator input is always the same (set by

the AGC), the squelch-offset requirement does not change

as the local noise strength changes from installation to

installation. Introducing squelch will reduce sensitivity and

also reduce range. Only introduce an amount of offset

sufficient to quiet the output. Typical squelch resistor

values range from 10MΩ to 6.8MΩ for low to high squelch

strength.

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF009

are diagrammed in Figures 2 through 8. The ESD

protection diodes at all input and output pins are not

shown.

CTH Pin

Figure 2. CTH Pin

Figure 2 illustrates the CTH pin interface circuit. The CTH

pin is driven from a P-Channel MOSFET source-follower

with approximately 10µA of bias. Transmission gates TG1

and TG2 isolate the 6.9pF capacitor. Internal control

signals PHI1/PHI2 are related in a manner such that the

impedance across the transmission gates looks like a

“resistance” of approximately 145kΩ. The DC potential at

the CTH pin is approximately 1.6V

CAGC Pin

Figure 3. CAGC Pin