Micrel

MICRF009

January 18, 2005

11

M9999-011805

(408) 955-1690

Figure 3 illustrates the CAGC pin interface circuit. The

AGC control voltage is developed as an integrated current

into a capacitor CAGC. The attack current is nominally

7µA, while the decay current is a 10 times scaling of this,

approximately 85µA. Signal gain of the RF/IF strip inside

the IC diminishes as the voltage on CAGC decreases. By

simply adding a capacitor to CAGC pin, the attack/decay

time constant ratio is fixed at 10:1. Modification of the

attack/decay ratio is possible by adding resistance from the

CAGC pin to either VDDBB or VSSBB, as desired.

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across CAGC, and

improves recovery time in duty-cycled applications. To

further improve duty-cycle recovery, both push and pull

currents are increased by 2 times for approximately 10ms

after release of the SHUT pin. This allows rapid recovery of

any voltage droop on CAGC while in shutdown.

DO Pin

The output stage for the digital output (DO) is shown in

Figure 4. The output is a 45µA push and 45µA pull

switched-current stage. This output stage is capable of

driving

CMOS

loads.

An

external

buffer-driver

is

recommended for driving high capacitance loads.

Figure 4. DO Pin

REFOSC1 and REFOSC2 Pin

The REFOSC input circuit is shown in Figure 5. Input

impedance is quite high (200kΩ). This is a Colpitts

oscillator, with internal 10pF capacitors. This input is

intended to work with standard crystal resonators,

connected from this pin to REFOSC2.

This REFOSC2 pin appears as a low resistance path to

VSS during normal operation and is an input to a buffer

amplifier used during the initial start up phase to ensure

rapid build up of crystal oscillations.

The resonators should not contain integral capacitors,

since these capacitors are contained inside the IC.

Externally

applied

signals

should

be

AC-coupled,

DC bias voltage on this pin is 1.4V

Figure 5. REFOSC Pin

SEL0, SEL1, SWEN, and SHUT Pins

Figure 6a. SEL0/SEL1/SWEN Pins

Figure 6b. SHUT Pin

Control input circuitry is shown in Figure 6a and 6b. The

standard input is a logic inverter constructed with minimum

geometry MOSFETs (Q2, Q3). P-Channel MOSFET Q1 is

a large channel length device, which functions essentially

as a “weak” pull-up to VDDBB. Typical pull-up current is

5µA, leading to an impedance to the VDDBB supply of

typically 1MΩ.