WM8591GEDSSLASHV datasheet(20/50 Pages) WOLFSON

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WM8591

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PP Rev 1.0 May 2005

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 12 Left Justified Mode Timing Diagram

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN is sampled by the WM8591 on the rising edge of DACBCLK

preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the

falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples

(Figure 13).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 13 Right Justified Mode Timing Diagram

2S MODE

In I

2S mode, the MSB of DIN is sampled by the WM8591 on the second rising edge of DACBCLK

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising

edge of ADCBCLK. ADCLRC and DACLRC are low during the left samples and high during the right

samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 14 I

2S Mode Timing Diagram

WM8591GEDS/V 数据表(PDF) 20 Page - Wolfson Microelectronics plc

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WM8591GEDS/V 数据表(PDF) 20 Page - Wolfson Microelectronics plc

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