WM8591GEDSSLASHV datasheet(31/50 Pages) WOLFSON

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WM8591

PP Rev 1.0 May 2005

Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to

write the same attenuation value to both left and right volume control registers, saving on software

writes. The ADC volume and mute also applies to the bypass signal path.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

LAG[7:0]

11001111

(0dB)

Attenuation Data for Left Channel ADC Gain in 0.5dB steps. See

Table 12.

R14 (0Eh)

0001110

Attenuation

ADCL

ZCLA

Left Channel ADC Zero Cross Enable:

0: Zero cross disabled

1: Zero cross enabled

7:0

RAG[7:0]

11001111

(0dB)

Attenuation data for right channel ADC gain in 0.5dB steps. See

Table 12.

R15 (0Fh)

0001111

Attenuation

ADCR

ZCRA

Right Channel ADC Zero Cross Enable:

0: Zero cross disabled

1: Zero cross enabled

MUTERA

Mute for Right Channel ADC

0: Mute Off

1: Mute on

MUTELA

Mute for Left Channel ADC

0: Mute Off

1: Mute on

R21 (15h)

0010101

ADC Input Mux

LRBOTH

Right Channel Input PGA Controlled by Left Channel Register

0: Right channel uses RAG and MUTERA

1: Right channel uses LAG and MUTELA

WM8591GEDS/V 数据表(PDF) 31 Page - Wolfson Microelectronics plc

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