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WM8718EDS/R 数据表(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8718EDS/R 数据表(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 27 page  WM8718 Production Data w PD Rev 4.1 March 2004 9 3-WIRE SERIAL CONTROL INTERFACE TIMING LATCH SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to LATCH rising edge tSCS 40 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 20 ns SCLK pulse width high tSCH 20 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns LATCH pulse width low tCSL 20 ns LATCH pulse width high tCSH 20 ns LATCH rising to SCLK rising tCSS 20 ns |
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