WM8718

Production Data

w

PD Rev 4.1 March 2004

13

MASTER CLOCK FREQUENCY (MHZ) (MCLK)

SAMPLING

RATE

(LRCIN)

128fs

192fs

256fs

384fs

512fs

768fs

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.144

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

Unavailable

Unavailable

192kHz

24.576

36.864

Unavailable

Unavailable

Unavailable

Unavailable

Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate

SOFTWARE CONTROL INTERFACE

The software control interface may be operated using a 3-wire (SPI-compatible) interface. In this

mode, SDIN is used for the program data, SCLK is used to clock in the program data and LATCH

is used to latch in the program data. The 3-wire interface protocol is shown in Figure 9.

LATCH

SCLK

SDIN

A6

D6

D7

D8

A0

A1

A2

A3

A4

A5

D1

D2

D3

D4

D5

D0

Figure 9 3-Wire Serial Control Interface

Notes:

1.

A[6:0] are Control Address Bits

2.

D[8:0] are Control Data Bits